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Searched refs:HiReg (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td346 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
364 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
368 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
390 (S2_vtrunewh (vmpyh (HiReg $Rs), (HiReg $Rt)),
394 (S2_vtrunewh (vmpyh (HiReg (S2_vsxtbh $Rs)), (HiReg (S2_vsxtbh $Rt))),
407 (A2_combinew (S2_vtrunehb (M5_vmpybsu (HiReg $Rs), (HiReg $Rt))),
412 (A2_combinew (S2_vtrunehb (VMPYB_no_V5 (HiReg $Rs), (HiReg $Rt))),
459 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
DHexagonCopyToCombine.cpp631 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
639 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
648 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
659 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
667 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
DHexagonInstrInfo.td32 def HiReg: OutPatFrag<(ops node:$Rs),
4974 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
4975 (HiReg DoubleRegs:$src3)),
5097 (HiReg $src1),
5100 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
5102 (HiReg $src1),
5103 (HiReg $src2)),
5104 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
DHexagonIntrinsics.td682 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2315 unsigned SrcReg, LoReg, HiReg; in Select() local
2320 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select()
2324 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select()
2328 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
2332 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
2335 SrcReg = X86::EDX; LoReg = HiReg = 0; in Select()
2338 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select()
2391 if (HiReg == X86::AH && Subtarget->is64Bit() && in Select()
2424 assert(HiReg && "Register for high half is not defined!"); in Select()
2425 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, in Select()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp286 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
302 std::swap(LoReg, HiReg); in expandBuildPairF64()
305 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
DMipsSEInstrInfo.cpp555 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
600 .addReg(HiReg); in expandBuildPairF64()
605 .addReg(HiReg); in expandBuildPairF64()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp5989 unsigned HiReg, bool &containsReg) { in checkLowRegisterList() argument
5996 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp8467 unsigned HiReg = MI->getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
8469 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
8476 .addReg(HiReg).addReg(ReadAgainReg); in EmitInstrWithCustomInserter()