| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsics.td | 21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
38 (MI ImmPred:$Is, I32:$Rt)>;
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
[all …]
|
| D | HexagonInstrInfoVector.td | 95 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
99 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
183 : Pat <(Op Value:$Rs, I32:$Rt),
184 (MI Value:$Rs, I32:$Rt)>;
352 def: Pat<(i64 (HexagonVSXTBH I32:$Rs)), (S2_vsxtbh I32:$Rs)>;
353 def: Pat<(i64 (HexagonVSXTBW I32:$Rs)), (S2_vsxthw I32:$Rs)>;
458 def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
459 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
462 def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
463 (S2_storeri_io I32:$Rt, 0, (S2_vtrunehb V4I16:$Rs))>;
[all …]
|
| D | HexagonInstrInfo.td | 23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
418 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
419 (i32 (A2_addi I32:$Rs, imm:$s16))>;
693 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
694 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
696 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
697 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
[all …]
|
| D | HexagonInstrInfoV5.td | 129 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
619 uint_to_fp, F32, I32>;
621 sint_to_fp, F32, I32>;
627 uint_to_fp, F64, I32>;
629 sint_to_fp, F64, I32>;
633 fp_to_uint, I32, F64, ":chop">;
635 fp_to_sint, I32, F64, ":chop">;
637 fp_to_uint, I32, F32, ":chop">;
639 fp_to_sint, I32, F32, ":chop">;
660 fp_to_uint, I32, F64>;
[all …]
|
| D | HexagonInstrInfoV4.td | 1018 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1019 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1020 def: Storexs_pat<store, I32, S4_storeri_rr>;
2382 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2383 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2384 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2385 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2386 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2387 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2614 (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
[all …]
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| /external/llvm/test/Transforms/ArgumentPromotion/ |
| D | reserve-tbaa.ll | 28 ; CHECK: store i32 1, i32* %{{.*}}, align 4, !tbaa ![[I32:[0-9]+]]
29 ; CHECK: %g.val = load i32, i32* @g, align 4, !tbaa ![[I32]]
49 ; CHECK: ![[I32]] = !{![[I32_TYPE:[0-9]+]], ![[I32_TYPE]], i64 0}
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCLoopDataPrefetch.cpp | 218 Type *I32 = Type::getInt32Ty((*I)->getContext()); in runOnLoop() local
221 ConstantInt::get(I32, MemI->mayReadFromMemory() ? 0 : 1), in runOnLoop()
222 ConstantInt::get(I32, 3), ConstantInt::get(I32, 1)); in runOnLoop()
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nouveau_render_t.c | 117 EMIT_VBO(I32, ctx, start, delta, n); in dispatch_i32()
127 EMIT_VBO(I32, ctx, start, delta, n & 1); in dispatch_i16()
|
| /external/valgrind/none/tests/amd64/ |
| D | rcl-amd64.c | 5 #define I32(C) "rcrl %%ebx\n" "rcll $" #C ",%%eax\n" "rcll %%ebx\n" macro
17 asm(I32(C) : "+a"(a), "+b"(b) : /* */); \
|
| /external/llvm/tools/llvm-stress/ |
| D | llvm-stress.cpp | 441 Type *I32 = Type::getInt32Ty(BB->getContext()); in Act() local
443 Constant *CI = ConstantInt::get(I32, Ran->Rand() % (Width*2)); in Act()
446 CI = UndefValue::get(I32); in Act()
|
| /external/llvm/test/CodeGen/R600/ |
| D | 32-bit-local-address-space.ll | 10 ; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 219 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
231 def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
261 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
274 def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
|
| D | X86ISelDAGToDAG.cpp | 1606 I32, enumerator
1833 Opc = AtomicOpcTbl[Op][I32]; in SelectAtomicLoadArith()
|
| /external/valgrind/VEX/orig_x86/ |
| D | manyfp.orig | 6098 vex iropt: fold_Expr: no rule for: 32to1(0x1:I32)
6242 vex iropt: fold_Expr: no rule for: 32to1(0x1:I32)
|
| /external/robolectric/lib/main/ |
| D | android.jar | META-INF/
META-INF/MANIFEST.MF
com/
com/android/
com/ ... |