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Searched refs:INTEL_MSAA_LAYOUT_NONE (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_blorp_blit.cpp626 assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) == in compile()
628 assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) == in compile()
630 assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) == in compile()
632 assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) == in compile()
1020 case INTEL_MSAA_LAYOUT_NONE: in encode_msaa()
1107 case INTEL_MSAA_LAYOUT_NONE: in decode_msaa()
1424 case INTEL_MSAA_LAYOUT_NONE: in texel_fetch()
1615 assert(true_layout == INTEL_MSAA_LAYOUT_NONE || in compute_msaa_layout_for_pipeline()
1617 return INTEL_MSAA_LAYOUT_NONE; in compute_msaa_layout_for_pipeline()
1619 assert(true_layout != INTEL_MSAA_LAYOUT_NONE); in compute_msaa_layout_for_pipeline()
Dbrw_tex_layout.c176 case INTEL_MSAA_LAYOUT_NONE: in brw_miptree_layout()
Dintel_mipmap_tree.c114 case INTEL_MSAA_LAYOUT_NONE: in intel_miptree_create_internal()
138 num_samples > 1 ? INTEL_MSAA_LAYOUT_IMS : INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_internal()
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) { in intel_miptree_create()
290 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_region()
403 enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_for_renderbuffer()
Dintel_tex_validate.c92 INTEL_MSAA_LAYOUT_NONE); in intel_finalize_mipmap_tree()
Dintel_tex_image.c104 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_teximage()
Dbrw_wm_surface_state.c1154 INTEL_MSAA_LAYOUT_NONE); in brw_update_renderbuffer_surface()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_mipmap_tree.c114 case INTEL_MSAA_LAYOUT_NONE: in intel_miptree_create_internal()
138 num_samples > 1 ? INTEL_MSAA_LAYOUT_IMS : INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_internal()
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) { in intel_miptree_create()
290 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_region()
403 enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_for_renderbuffer()
Dintel_tex_validate.c92 INTEL_MSAA_LAYOUT_NONE); in intel_finalize_mipmap_tree()
Dintel_tex_image.c104 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_teximage()
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_mipmap_tree.c114 case INTEL_MSAA_LAYOUT_NONE: in intel_miptree_create_internal()
138 num_samples > 1 ? INTEL_MSAA_LAYOUT_IMS : INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_internal()
217 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) { in intel_miptree_create()
290 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_region()
403 enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_for_renderbuffer()
Dintel_tex_validate.c92 INTEL_MSAA_LAYOUT_NONE); in intel_finalize_mipmap_tree()
Dintel_mipmap_tree.h155 INTEL_MSAA_LAYOUT_NONE, enumerator
Dintel_tex_image.c104 INTEL_MSAA_LAYOUT_NONE); in intel_miptree_create_for_teximage()