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Searched refs:MCOperand (Results 1 – 25 of 112) sorted by relevance

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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp493 MI.addOperand(MCOperand::CreateImm(tmp)); in DecodeINSVE_DF()
499 MI.addOperand(MCOperand::CreateImm(0)); in DecodeINSVE_DF()
533 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
536 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
538 MI.addOperand(MCOperand::CreateImm(Imm)); in DecodeAddiGroupBranch()
572 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
575 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
577 MI.addOperand(MCOperand::CreateImm(Imm)); in DecodeDaddiGroupBranch()
614 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
617 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
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/external/llvm/include/llvm/MC/
DMCInst.h33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand CreateReg(unsigned Reg) { in CreateReg()
112 MCOperand Op; in CreateReg()
117 static MCOperand CreateImm(int64_t Val) { in CreateImm()
118 MCOperand Op; in CreateImm()
123 static MCOperand CreateFPImm(double Val) { in CreateFPImm()
124 MCOperand Op; in CreateFPImm()
129 static MCOperand CreateExpr(const MCExpr *Val) { in CreateExpr()
130 MCOperand Op; in CreateExpr()
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DMCInstBuilder.h33 Inst.addOperand(MCOperand::CreateReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::CreateImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::CreateFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::CreateExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::CreateInst(Val)); in addInst()
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp79 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
84 return MCOperand::CreateExpr(expr); in createSparcMCOperand()
87 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
92 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
107 return MCOperand::CreateExpr(expr); in createPCXRelExprOp()
111 MCOperand &Callee, in EmitCall()
121 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
144 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
150 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
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DSparcMCInstLower.cpp31 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
66 return MCOperand::CreateExpr(expr); in LowerSymbolOperand()
69 static MCOperand LowerOperand(const MachineInstr *MI, in LowerOperand()
77 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
80 return MCOperand::CreateImm(MO.getImm()); in LowerOperand()
92 return MCOperand(); in LowerOperand()
104 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerSparcMachineInstrToMCInst()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
277 const MCOperand &MO = MI.getOperand(Op); in getSOImmOpValue()
310 const MCOperand &MO = MI.getOperand(Op); in getModImmOpValue()
529 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
561 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
591 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
628 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
641 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
653 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBRTargetOpValue()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp115 const MCOperand &Dst = MI->getOperand(0); in printInst()
116 const MCOperand &MO1 = MI->getOperand(1); in printInst()
117 const MCOperand &MO2 = MI->getOperand(2); in printInst()
118 const MCOperand &MO3 = MI->getOperand(3); in printInst()
138 const MCOperand &Dst = MI->getOperand(0); in printInst()
139 const MCOperand &MO1 = MI->getOperand(1); in printInst()
140 const MCOperand &MO2 = MI->getOperand(2); in printInst()
282 MCOperand NewReg; in printInst()
287 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg( in printInst()
321 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp183 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
251 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); in translateSrcIndex()
254 MCOperand segmentReg; in translateSrcIndex()
255 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
276 MCOperand baseReg = MCOperand::CreateReg(baseRegNo); in translateDstIndex()
542 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
545 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
548 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
571 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
575 MCOperand segmentReg; in translateImmediate()
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
213 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
227 const MCOperand &MO = MI.getOperand(OpIdx); in getLdStUImm12OpValue()
248 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrLabelOpValue()
275 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
276 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue()
301 const MCOperand &MO = MI.getOperand(OpIdx); in getCondBranchTargetOpValue()
323 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLiteralOpValue()
352 const MCOperand &MO = MI.getOperand(OpIdx); in getMoveWideImmOpValue()
371 const MCOperand &MO = MI.getOperand(OpIdx); in getTestBranchTargetOpValue()
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/external/llvm/lib/Target/XCore/
DXCoreMCInstLower.cpp35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
71 return MCOperand::CreateExpr(MCSym); in LowerSymbolOperand()
78 return MCOperand::CreateExpr(Add); in LowerSymbolOperand()
81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
90 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
92 return MCOperand::CreateImm(MO.getImm() + offset); in LowerOperand()
104 return MCOperand(); in LowerOperand()
112 MCOperand MCOp = LowerOperand(MO); in Lower()
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp55 Inst.addOperand(MCOperand::CreateReg(RegNo)); in decodeRegisterClass()
110 Inst.addOperand(MCOperand::CreateImm(Imm)); in decodeUImmOperand()
117 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
171 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address)); in decodePCDBLOperand()
192 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
193 Inst.addOperand(MCOperand::CreateImm(Disp)); in decodeBDAddr12Operand()
202 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
203 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
213 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
214 Inst.addOperand(MCOperand::CreateImm(Disp)); in decodeBDXAddr12Operand()
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/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp523 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); in addRegGPRCOperands()
528 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
533 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); in addRegG8RCOperands()
538 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
557 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF4RCOperands()
562 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); in addRegF8RCOperands()
567 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); in addRegVRRCOperands()
572 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
577 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
582 Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()])); in addRegQFRCOperands()
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/external/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp33 MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
41 return MCOperand::CreateExpr(Expr); in LowerSymbolOperand()
50 MCOperand MCOp; in Lower()
59 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
62 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
65 MCOp = MCOperand::CreateExpr( in Lower()
/external/llvm/lib/Target/Hexagon/
DHexagonMCInstLower.cpp26 static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol, in GetSymbolRef()
37 return (MCOperand::CreateExpr(ME)); in GetSymbolRef()
47 MCOperand MCO; in HexagonLowerToMC()
56 MCO = MCOperand::CreateReg(MO.getReg()); in HexagonLowerToMC()
62 MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData()); in HexagonLowerToMC()
66 MCO = MCOperand::CreateImm(MO.getImm()); in HexagonLowerToMC()
69 MCO = MCOperand::CreateExpr in HexagonLowerToMC()
/external/llvm/lib/Target/AArch64/
DAArch64MCInstLower.h21 class MCOperand; variable
38 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
41 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
43 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
45 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
DAArch64MCInstLower.cpp44 MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO, in lowerSymbolOperandDarwin()
76 return MCOperand::CreateExpr(Expr); in lowerSymbolOperandDarwin()
79 MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO, in lowerSymbolOperandELF()
151 return MCOperand::CreateExpr(Expr); in lowerSymbolOperandELF()
154 MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
164 MCOperand &MCOp) const { in lowerOperand()
172 MCOp = MCOperand::CreateReg(MO.getReg()); in lowerOperand()
178 MCOp = MCOperand::CreateImm(MO.getImm()); in lowerOperand()
181 MCOp = MCOperand::CreateExpr( in lowerOperand()
208 MCOperand MCOp; in Lower()
/external/llvm/lib/Target/ARM/
DARMMCInstLower.cpp27 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, in GetSymbolRef()
64 return MCOperand::CreateExpr(Expr); in GetSymbolRef()
69 MCOperand &MCOp) { in lowerOperand()
77 MCOp = MCOperand::CreateReg(MO.getReg()); in lowerOperand()
80 MCOp = MCOperand::CreateImm(MO.getImm()); in lowerOperand()
83 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in lowerOperand()
108 MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); in lowerOperand()
153 MCOperand MCOp; in LowerARMMachineInstrToMCInst()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp689 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
691 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
693 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
705 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg())); in addGPR32AsmRegOperands()
710 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegOperands()
715 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegZeroOperands()
720 Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); in addGPRMM16AsmRegMovePOperands()
728 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg())); in addGPR64AsmRegOperands()
733 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg())); in addAFGR64AsmRegOperands()
738 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg())); in addFGR64AsmRegOperands()
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/external/llvm/lib/Target/Mips/
DMipsMCInstLower.cpp36 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
107 return MCOperand::CreateExpr(MCSym); in LowerSymbolOperand()
114 return MCOperand::CreateExpr(Add); in LowerSymbolOperand()
129 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
138 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
140 return MCOperand::CreateImm(MO.getImm() + offset); in LowerOperand()
152 return MCOperand(); in LowerOperand()
155 MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1, in createSub()
162 return MCOperand::CreateExpr(MipsMCExpr::Create(Kind, Sub, *Ctx)); in createSub()
228 MCOperand MCOp = LowerOperand(MO); in Lower()
/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp125 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm()
146 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
162 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); in printMemReference()
163 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); in printMemReference()
211 const MCOperand &SegReg = MI->getOperand(Op+1); in printSrcIdx()
233 const MCOperand &DispSpec = MI->getOperand(Op); in printMemOffset()
234 const MCOperand &SegReg = MI->getOperand(Op+1); in printMemOffset()
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp91 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
173 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
185 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
198 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
211 const MCOperand &MO = MI.getOperand(OpNo); in getAbsCondBrEncoding()
223 const MCOperand &MO = MI.getOperand(OpNo); in getImm16Encoding()
240 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIEncoding()
259 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIXEncoding()
279 const MCOperand &MO = MI.getOperand(OpNo); in getSPE8DisEncoding()
295 const MCOperand &MO = MI.getOperand(OpNo); in getSPE4DisEncoding()
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1753 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
1755 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
1757 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
1762 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
1764 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1769 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocNumOperands()
1774 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocRegOperands()
1779 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); in addCoprocOptionOperands()
1784 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); in addITMaskOperands()
1789 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
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/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
590 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
649 I = MI.insert(I, MCOperand::CreateImm(CC)); in AddThumbPredicate()
652 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
659 I = MI.insert(I, MCOperand::CreateImm(CC)); in AddThumbPredicate()
662 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
664 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
897 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
921 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp700 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
703 TmpInst.addOperand(MCOperand::CreateExpr(HiSym)); in emitDirectiveCpLoad()
709 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
710 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
713 TmpInst.addOperand(MCOperand::CreateExpr(LoSym)); in emitDirectiveCpLoad()
719 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
720 TmpInst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpLoad()
721 TmpInst.addOperand(MCOperand::CreateReg(RegNo)); in emitDirectiveCpLoad()
742 Inst.addOperand(MCOperand::CreateReg(RegOrOffset)); in emitDirectiveCpsetup()
743 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); in emitDirectiveCpsetup()
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/external/llvm/lib/Target/R600/
DAMDGPUMCInstLower.cpp56 MCOperand MCOp; in lower()
61 MCOp = MCOperand::CreateImm(MO.getImm()); in lower()
64 MCOp = MCOperand::CreateReg(MO.getReg()); in lower()
67 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( in lower()
73 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(Sym, Ctx)); in lower()
80 MCOp = MCOperand::CreateExpr(Expr); in lower()
86 MCOp = MCOperand::CreateExpr(Expr); in lower()

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