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Searched refs:MCSchedClassDesc (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetSchedule.cpp77 const MCSchedClassDesc *SC) const { in getNumMicroOps()
101 const MCSchedClassDesc *TargetSchedModel::
106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
199 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
231 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx); in computeInstrLatency()
259 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
299 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
DMachineCombiner.cpp79 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
258 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
262 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
280 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
281 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
286 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC); in preservesResourceLen()
287 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC); in preservesResourceLen()
DMachineTraceMetrics.cpp109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1194 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1195 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1202 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1207 const MCSchedClassDesc *SC = Instrs[I]; in getResourceLength()
DMachineScheduler.cpp1626 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init()
1707 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
1910 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2135 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
DScheduleDAGInstrs.cpp724 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h55 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
89 const MCSchedClassDesc *SC = nullptr) const;
113 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
117 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
DMachineTraceMetrics.h268 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
269 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
DScheduleDAGInstrs.h172 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
DScheduleDAG.h33 struct MCSchedClassDesc;
272 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
/external/llvm/include/llvm/MC/
DMCSubtargetInfo.h104 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
108 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
112 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
120 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
DMCSchedule.h101 struct MCSchedClassDesc { struct
193 const MCSchedClassDesc *SchedClassTable;
220 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp38 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
824 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); in GenSchedClassTables()
830 MCSchedClassDesc &SCDesc = SCTab.back(); in GenSchedClassTables()
856 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
939 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
989 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1011 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1132 std::vector<MCSchedClassDesc> &SCTab = in EmitSchedClassTables()
1145 << MCSchedClassDesc::InvalidNumMicroOps in EmitSchedClassTables()
1149 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()
/external/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp82 const MCSchedClassDesc *SCDesc = in shouldAddSTPToBlock()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp197 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()