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Searched refs:MUL (Results 1 – 25 of 212) sorted by relevance

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/external/llvm/test/Transforms/InstCombine/
Doverflow-mul.ll11 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
13 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
26 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
28 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
42 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
44 ; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
46 ; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
74 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
76 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
90 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll2 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
9 ; MUL: mul.rn.f32
10 ; MUL: add.rn.f32
19 ; MUL: mul.rn.f64
20 ; MUL: add.rn.f64
/external/llvm/test/CodeGen/R600/
Dllvm.sqrt.ll7 ; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS
19 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS
21 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS
34 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS
36 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS
38 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS
40 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS
Dllvm.pow.ll5 ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
19 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
21 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
25 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
27 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
Dmul_uint24.ll26 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
27 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16
40 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
41 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
Dfdiv.f64.ll26 ; COMMON-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[SCALE1]], [[FMA3]]
27 ; COMMON-DAG: v_fma_f64 [[FMA4:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[MUL]], [[SCALE1]]
28 ; COMMON: v_div_fmas_f64 [[FMAS:v\[[0-9]+:[0-9]+\]]], [[FMA4]], [[FMA3]], [[MUL]]
Dfp_to_sint.f64.ll40 ; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
41 ; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
/external/v8/src/ic/
Dic-state.cc200 GENERATE(Token::MUL, INT32, INT32, INT32, NO_OVERWRITE); in GenerateAheadOfTime()
201 GENERATE(Token::MUL, INT32, INT32, NUMBER, NO_OVERWRITE); in GenerateAheadOfTime()
202 GENERATE(Token::MUL, INT32, NUMBER, NUMBER, NO_OVERWRITE); in GenerateAheadOfTime()
203 GENERATE(Token::MUL, INT32, NUMBER, NUMBER, OVERWRITE_LEFT); in GenerateAheadOfTime()
204 GENERATE(Token::MUL, INT32, SMI, INT32, NO_OVERWRITE); in GenerateAheadOfTime()
205 GENERATE(Token::MUL, INT32, SMI, INT32, OVERWRITE_LEFT); in GenerateAheadOfTime()
206 GENERATE(Token::MUL, INT32, SMI, NUMBER, NO_OVERWRITE); in GenerateAheadOfTime()
207 GENERATE(Token::MUL, NUMBER, INT32, NUMBER, NO_OVERWRITE); in GenerateAheadOfTime()
208 GENERATE(Token::MUL, NUMBER, INT32, NUMBER, OVERWRITE_LEFT); in GenerateAheadOfTime()
209 GENERATE(Token::MUL, NUMBER, INT32, NUMBER, OVERWRITE_RIGHT); in GenerateAheadOfTime()
[all …]
/external/tremolo/Tremolo/
DmdctLARM.s202 MUL r11,r12,r11 @ r11 = *l * *wL++
242 MUL r11,r12,r11 @ (r14,r11) = *l * *wL++
244 MUL r6, r7, r6 @ (r14,r6) = *--r * *--wR
327 MUL r9, r6, r10 @ r9 = s0*T[0]
331 MUL r12,r7, r10 @ r12 = s2*T[0]
347 MUL r9, r6, r10 @ r9 = s0*T[1]
351 MUL r12,r7, r10 @ r12 = s2*T[1]
379 MUL r12,r8, r11 @ r12 = ro0*T[1]
383 MUL r3, r9, r11 @ r3 = ro2*T[1]
392 MUL r12,r6, r10 @ r12 = ri0*T[0]
[all …]
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-flr.sh11 MUL TEMP[0], IN[0], IMM[0]
13 MUL OUT[0], TEMP[0], IMM[1]
Dfrag-mul.sh8 MUL OUT[0], IN[0], IMM[0]
Dfrag-ex2.sh9 MUL OUT[0], TEMP[0], IN[0]
Dfrag-frc.sh10 MUL TEMP[0], IN[0], IMM[0]
Dfrag-sge.sh11 MUL OUT[0], IN[0], TEMP[0]
Dfrag-slt.sh11 MUL OUT[0], IN[0], TEMP[0]
Dfrag-srcmod-absneg.sh13 MUL OUT[0], TEMP[0], IMM[1]
Dfrag-cb-1d.sh11 MUL OUT[0], TEMP[0], TEMP[1]
/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-ex2.sh14 MUL TEMP[0], TEMP[0], IMM[0]
16 MUL OUT[1], TEMP[0], TEMP[1]
Dvert-mul.sh10 MUL OUT[0], IN[0], IMM[0]
Dvert-frc.sh11 MUL TEMP[0], IN[0].xyxw, IMM[0]
Dvert-slt.sh14 MUL OUT[1], IN[1], TEMP[0]
/external/webp/src/dsp/
Ddec.c39 #define MUL(a, b) (((a) * (b)) >> 16) macro
48 const int c = MUL(in[4], kC2) - MUL(in[12], kC1); // [-3783, 3783] in TransformOne()
49 const int d = MUL(in[4], kC1) + MUL(in[12], kC2); // [-3785, 3781] in TransformOne()
69 const int c = MUL(tmp[4], kC2) - MUL(tmp[12], kC1); in TransformOne()
70 const int d = MUL(tmp[4], kC1) + MUL(tmp[12], kC2); in TransformOne()
83 const int c4 = MUL(in[4], kC2); in TransformAC3()
84 const int d4 = MUL(in[4], kC1); in TransformAC3()
85 const int c1 = MUL(in[1], kC2); in TransformAC3()
86 const int d1 = MUL(in[1], kC1); in TransformAC3()
92 #undef MUL
Denc.c90 #define MUL(a, b) (((a) * (b)) >> 16) macro
100 const int c = MUL(in[4], kC2) - MUL(in[12], kC1); in ITransformOne()
101 const int d = MUL(in[4], kC1) + MUL(in[12], kC2); in ITransformOne()
115 const int c = MUL(tmp[4], kC2) - MUL(tmp[12], kC1); in ITransformOne()
116 const int d = MUL(tmp[4], kC1) + MUL(tmp[12], kC2); in ITransformOne()
192 #undef MUL
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
DRegOps.java89 public static final int MUL = 16; field in RegOps
329 case MUL: return "mul"; in opName()
/external/antlr/antlr-3.4/runtime/Python/tests/
Dt048rewrite2.g10 MUL : '*';

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