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Searched refs:Mask (Results 1 – 25 of 270) sorted by relevance

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/external/v8/src/arm64/
Ddecoder-arm64-inl.h132 (instr->Mask(0x01000010) == 0x00000010)) { in DecodeBranchSystemException()
146 (instr->Mask(0x00E0001D) == 0x00200001) || in DecodeBranchSystemException()
147 (instr->Mask(0x00E0001D) == 0x00400001) || in DecodeBranchSystemException()
148 (instr->Mask(0x00E0001E) == 0x00200002) || in DecodeBranchSystemException()
149 (instr->Mask(0x00E0001E) == 0x00400002) || in DecodeBranchSystemException()
150 (instr->Mask(0x00E0001C) == 0x00600000) || in DecodeBranchSystemException()
151 (instr->Mask(0x00E0001C) == 0x00800000) || in DecodeBranchSystemException()
152 (instr->Mask(0x00E0001F) == 0x00A00000) || in DecodeBranchSystemException()
153 (instr->Mask(0x00C0001C) == 0x00C00000)) { in DecodeBranchSystemException()
160 const Instr masked_003FF0E0 = instr->Mask(0x003FF0E0); in DecodeBranchSystemException()
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Dinstructions-arm64.h120 Instr Mask(uint32_t mask) const { in Mask() function
152 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask))); in SizeLSPair()
157 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed; in IsCondBranchImm()
161 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed; in IsUncondBranchImm()
165 return Mask(CompareBranchFMask) == CompareBranchFixed; in IsCompareBranch()
169 return Mask(TestBranchFMask) == TestBranchFixed; in IsTestBranch()
177 return Mask(LoadLiteralFMask) == LoadLiteralFixed; in IsLdrLiteral()
181 return Mask(LoadLiteralMask) == LDR_x_lit; in IsLdrLiteralX()
185 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed; in IsPCRelAddressing()
189 return Mask(PCRelAddressingMask) == ADR; in IsAdr()
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Ddisasm-arm64.cc61 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
105 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
153 switch (instr->Mask(AddSubExtendedMask)) { in VisitAddSubExtended()
188 switch (instr->Mask(AddSubWithCarryMask)) { in VisitAddSubWithCarry()
229 switch (instr->Mask(LogicalImmediateMask)) { in VisitLogicalImmediate()
295 switch (instr->Mask(LogicalShiftedMask)) { in VisitLogicalShifted()
344 switch (instr->Mask(ConditionalCompareRegisterMask)) { in VisitConditionalCompareRegister()
359 switch (instr->Mask(ConditionalCompareImmediateMask)) { in VisitConditionalCompareImmediate()
381 switch (instr->Mask(ConditionalSelectMask)) { in VisitConditionalSelect()
436 switch (instr->Mask(BitfieldMask)) { in VisitBitfield()
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Dinstructions-arm64.cc19 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) { in IsLoad()
23 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) { in IsLoad()
24 return Mask(LoadStorePairLBit) != 0; in IsLoad()
26 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreOpMask)); in IsLoad()
46 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) { in IsStore()
50 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) { in IsStore()
51 return Mask(LoadStorePairLBit) == 0; in IsStore()
53 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreOpMask)); in IsStore()
240 SetInstructionBits(Mask(~ImmPCRel_mask) | imm); in SetPCRelImmTarget()
277 SetInstructionBits(Mask(~imm_mask) | branch_imm); in SetBranchImmTarget()
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/external/vixl/src/vixl/a64/
Ddecoder-a64.cc192 (instr->Mask(0x01000010) == 0x00000010)) { in DecodeBranchSystemException()
206 (instr->Mask(0x00E0001D) == 0x00200001) || in DecodeBranchSystemException()
207 (instr->Mask(0x00E0001D) == 0x00400001) || in DecodeBranchSystemException()
208 (instr->Mask(0x00E0001E) == 0x00200002) || in DecodeBranchSystemException()
209 (instr->Mask(0x00E0001E) == 0x00400002) || in DecodeBranchSystemException()
210 (instr->Mask(0x00E0001C) == 0x00600000) || in DecodeBranchSystemException()
211 (instr->Mask(0x00E0001C) == 0x00800000) || in DecodeBranchSystemException()
212 (instr->Mask(0x00E0001F) == 0x00A00000) || in DecodeBranchSystemException()
213 (instr->Mask(0x00C0001C) == 0x00C00000)) { in DecodeBranchSystemException()
220 const Instr masked_003FF0E0 = instr->Mask(0x003FF0E0); in DecodeBranchSystemException()
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Ddisasm-a64.cc71 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
115 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
163 switch (instr->Mask(AddSubExtendedMask)) { in VisitAddSubExtended()
198 switch (instr->Mask(AddSubWithCarryMask)) { in VisitAddSubWithCarry()
239 switch (instr->Mask(LogicalImmediateMask)) { in VisitLogicalImmediate()
305 switch (instr->Mask(LogicalShiftedMask)) { in VisitLogicalShifted()
354 switch (instr->Mask(ConditionalCompareRegisterMask)) { in VisitConditionalCompareRegister()
369 switch (instr->Mask(ConditionalCompareImmediateMask)) { in VisitConditionalCompareImmediate()
391 switch (instr->Mask(ConditionalSelectMask)) { in VisitConditionalSelect()
446 switch (instr->Mask(BitfieldMask)) { in VisitBitfield()
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Dinstructions-a64.cc75 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) { in IsLoad()
79 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) { in IsLoad()
80 return Mask(LoadStorePairLBit) != 0; in IsLoad()
82 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask)); in IsLoad()
105 if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) { in IsStore()
109 if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) { in IsStore()
110 return Mask(LoadStorePairLBit) == 0; in IsStore()
112 LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask)); in IsStore()
301 if (Mask(PCRelAddressingMask) == ADRP) { in ImmPCOffsetTarget()
305 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in ImmPCOffsetTarget()
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Dinstructions-a64.h186 Instr Mask(uint32_t mask) const { in Mask() function
211 return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask))); in SizeLS()
216 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask))); in SizeLSPair()
229 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed; in IsCondBranchImm()
233 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed; in IsUncondBranchImm()
237 return Mask(CompareBranchFMask) == CompareBranchFixed; in IsCompareBranch()
241 return Mask(TestBranchFMask) == TestBranchFixed; in IsTestBranch()
249 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed; in IsPCRelAddressing()
253 return Mask(LogicalImmediateFMask) == LogicalImmediateFixed; in IsLogicalImmediate()
257 return Mask(AddSubImmediateFMask) == AddSubImmediateFixed; in IsAddSubImmediate()
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Dsimulator-a64.cc831 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) || in VisitPCRelAddressing()
832 (instr->Mask(PCRelAddressingMask) == ADRP)); in VisitPCRelAddressing()
839 switch (instr->Mask(UnconditionalBranchMask)) { in VisitUnconditionalBranch()
852 VIXL_ASSERT(instr->Mask(ConditionalBranchMask) == B_cond); in VisitConditionalBranch()
862 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { in VisitUnconditionalBranchToRegister()
878 switch (instr->Mask(TestBranchMask)) { in VisitTestBranch()
892 switch (instr->Mask(CompareBranchMask)) { in VisitCompareBranch()
909 Instr operation = instr->Mask(AddSubOpMask); in AddSubHelper()
967 if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) { in VisitAddSubWithCarry()
987 if (instr->Mask(NOT) == NOT) { in VisitLogicalShifted()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp331 SmallVectorImpl<Constant*> &Mask) { in CollectSingleShuffleElements() argument
337 Mask.assign(NumElts, UndefValue::get(Type::getInt32Ty(V->getContext()))); in CollectSingleShuffleElements()
343 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), i)); in CollectSingleShuffleElements()
349 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), in CollectSingleShuffleElements()
367 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { in CollectSingleShuffleElements()
369 Mask[InsertedIdx] = UndefValue::get(Type::getInt32Ty(V->getContext())); in CollectSingleShuffleElements()
382 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { in CollectSingleShuffleElements()
385 Mask[InsertedIdx % NumElts] = in CollectSingleShuffleElements()
390 Mask[InsertedIdx % NumElts] = in CollectSingleShuffleElements()
416 SmallVectorImpl<Constant *> &Mask, in CollectShuffleElements() argument
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DInstCombineShifts.cpp241 APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits)); in GetShiftedValue() local
243 ConstantInt::get(BO->getContext(), Mask)); in GetShiftedValue()
281 APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits)); in GetShiftedValue() local
283 ConstantInt::get(BO->getContext(), Mask)); in GetShiftedValue()
437 Constant *Mask = ConstantInt::get(I.getContext(), Bits); in FoldShiftByConstant() local
439 Mask = ConstantVector::getSplat(VT->getNumElements(), Mask); in FoldShiftByConstant()
440 return BinaryOperator::CreateAnd(X, Mask); in FoldShiftByConstant()
473 Constant *Mask = ConstantInt::get(I.getContext(), Bits); in FoldShiftByConstant() local
475 Mask = ConstantVector::getSplat(VT->getNumElements(), Mask); in FoldShiftByConstant()
476 return BinaryOperator::CreateAnd(X, Mask); in FoldShiftByConstant()
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/external/llvm/lib/Analysis/
DCostModel.cpp92 static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) { in isReverseVectorMask() argument
93 for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i) in isReverseVectorMask()
94 if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i)) in isReverseVectorMask()
99 static bool isAlternateVectorMask(SmallVectorImpl<int> &Mask) { in isAlternateVectorMask() argument
101 unsigned MaskSize = Mask.size(); in isAlternateVectorMask()
105 if (Mask[i] < 0) in isAlternateVectorMask()
107 isAlternate = Mask[i] == (int)((i & 1) ? MaskSize + i : i); in isAlternateVectorMask()
116 if (Mask[i] < 0) in isAlternateVectorMask()
118 isAlternate = Mask[i] == (int)((i & 1) ? i : MaskSize + i); in isAlternateVectorMask()
147 SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1); in matchPairwiseShuffleMask() local
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DAliasAnalysis.cpp65 AliasAnalysis::ModRefResult &Mask) { in getArgLocation() argument
67 return AA->getArgLocation(CS, ArgIdx, Mask); in getArgLocation()
112 ModRefResult Mask = ModRef; in getModRefInfo() local
114 Mask = Ref; in getModRefInfo()
137 Mask = ModRefResult(Mask & AllArgsMask); in getModRefInfo()
142 if ((Mask & Mod) && pointsToConstantMemory(Loc)) in getModRefInfo()
143 Mask = ModRefResult(Mask & ~Mod); in getModRefInfo()
146 if (!AA) return Mask; in getModRefInfo()
150 return ModRefResult(AA->getModRefInfo(CS, Loc) & Mask); in getModRefInfo()
168 AliasAnalysis::ModRefResult Mask = ModRef; in getModRefInfo() local
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/external/llvm/include/llvm/ADT/
DSmallBitVector.h307 uintptr_t Mask = EMask - IMask; in set() local
308 setSmallBits(getSmallBits() | Mask); in set()
338 uintptr_t Mask = EMask - IMask; in reset() local
339 setSmallBits(getSmallBits() & ~Mask); in reset()
519 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
521 applyMask<true, false>(Mask, MaskWords);
523 getPointer()->setBitsInMask(Mask, MaskWords);
528 void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
530 applyMask<false, false>(Mask, MaskWords);
532 getPointer()->clearBitsInMask(Mask, MaskWords);
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DBitVector.h240 BitWord Mask = EMask - IMask; in set() local
241 Bits[I / BITWORD_SIZE] |= Mask; in set()
279 BitWord Mask = EMask - IMask; in reset() local
280 Bits[I / BITWORD_SIZE] &= ~Mask; in reset()
318 BitWord Mask = BitWord(1) << (Idx % BITWORD_SIZE); variable
319 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
481 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
482 applyMask<true, false>(Mask, MaskWords);
487 void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
488 applyMask<false, false>(Mask, MaskWords);
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/external/llvm/utils/PerfectShuffle/
DPerfectShuffle.cpp35 static unsigned getMaskElt(unsigned Mask, unsigned Elt) { in getMaskElt() argument
36 return (Mask >> ((3-Elt)*4)) & 0xF; in getMaskElt()
39 static unsigned setMaskElt(unsigned Mask, unsigned Elt, unsigned NewVal) { in setMaskElt() argument
41 return (Mask & ~(0xF << FieldShift)) | (NewVal << FieldShift); in setMaskElt()
45 static bool isValidMask(unsigned short Mask) { in isValidMask() argument
46 unsigned short UndefBits = Mask & 0x8888; in isValidMask()
47 return (Mask & ((UndefBits >> 1)|(UndefBits>>2)|(UndefBits>>3))) == 0; in isValidMask()
52 static bool hasUndefElements(unsigned short Mask) { in hasUndefElements() argument
53 return (Mask & 0x8888) != 0; in hasUndefElements()
58 static bool isOnlyLHSMask(unsigned short Mask) { in isOnlyLHSMask() argument
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/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3097 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); in LowerCall() local
3098 assert(Mask && "Missing call preserved mask for calling convention"); in LowerCall()
3099 Ops.push_back(DAG.getRegisterMask(Mask)); in LowerCall()
3806 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, in isSequentialOrUndefInRange() argument
3809 if (!isUndefOrEqual(Mask[i], Low)) in isSequentialOrUndefInRange()
4097 SDValue Mask = DAG.getConstant(MaskVal, MVT::i8); in Insert128BitVector() local
4098 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask); in Insert128BitVector()
4113 SDValue Mask = DAG.getConstant(0x0f, MVT::i8); in Insert128BitVector() local
4115 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask); in Insert128BitVector()
4177 SmallVector<int, 8> Mask; in getMOVL() local
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/external/vboot_reference/utility/
Defidecompress.c218 UINT16 Mask; in MakeTable() local
261 Mask = (UINT16) (1U << (15 - TableBits)); in MakeTable()
290 if (Index3 & Mask) { in MakeTable()
334 UINT32 Mask; in DecodeP() local
340 Mask = 1U << (BITBUFSIZ - 1 - 8); in DecodeP()
344 if (Sd->mBitBuf & Mask) { in DecodeP()
350 Mask >>= 1; in DecodeP()
397 UINT32 Mask; in ReadPTLen() local
422 Mask = 1U << (BITBUFSIZ - 1 - 3); in ReadPTLen()
423 while (Mask & Sd->mBitBuf) { in ReadPTLen()
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/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp117 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), in RxSBGOperands()
122 uint64_t Mask; member
265 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const;
680 uint64_t Mask) const { in refineRxSBGMask()
683 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); in refineRxSBGMask()
684 Mask &= RxSBG.Mask; in refineRxSBGMask()
685 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { in refineRxSBGMask()
686 RxSBG.Mask = Mask; in refineRxSBGMask()
693 static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) { in maskMatters() argument
696 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); in maskMatters()
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/external/llvm/lib/CodeGen/
DStackMapLivenessAnalysis.cpp153 uint32_t *Mask = createRegisterMask(); in addLiveOutSetToMI() local
154 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask); in addLiveOutSetToMI()
162 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs()); in createRegisterMask() local
165 Mask[*RI / 32] |= 1U << (*RI % 32); in createRegisterMask()
167 TRI->adjustStackMapLiveOutMask(Mask); in createRegisterMask()
168 return Mask; in createRegisterMask()
DLiveRangeCalc.cpp67 unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate() local
79 unsigned Common = S.LaneMask & Mask; in calculate()
83 unsigned LRest = S.LaneMask & ~Mask; in calculate()
95 Mask &= ~Common; in calculate()
98 if (Mask != 0) { in calculate()
99 LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask); in calculate()
141 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, unsigned Mask) { in extendToUses() argument
152 if (Mask != ~0u) in extendToUses()
162 if ((SubRegMask & Mask) == 0) in extendToUses()
/external/clang/include/clang/AST/
DType.h162 Qualifiers() : Mask(0) {}
168 if (!(L.Mask & ~CVRMask) && !(R.Mask & ~CVRMask)) {
170 Q.Mask = L.Mask & R.Mask;
171 L.Mask &= ~Q.Mask;
172 R.Mask &= ~Q.Mask;
202 static Qualifiers fromFastMask(unsigned Mask) {
204 Qs.addFastQualifiers(Mask);
217 Qs.Mask = opaque;
223 return Mask;
226 bool hasConst() const { return Mask & Const; }
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DDeclAccessPair.h33 enum { Mask = 0x3 }; enumerator
43 return reinterpret_cast<NamedDecl*>(~Mask & Ptr); in getDecl()
46 return AccessSpecifier(Mask & Ptr); in getAccess()
/external/tcpdump/tests/
DQinQpacketv.out10 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
23 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
37 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
50 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
63 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
76 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
89 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
102 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
120 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
133 Subnet-Mask, Default-Gateway, Domain-Name-Server, NTP
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/external/llvm/lib/Fuzzer/
DFuzzerMutate.cpp18 char Mask = 1 << Bit; in FlipRandomBit() local
21 R = X & ~Mask; in FlipRandomBit()
23 R = X | Mask; in FlipRandomBit()

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