| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 84 unsigned NumRegs = RC->getNumRegs(); in compute() local
87 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
116 RCI.NumRegs = N + CSRAlias.size(); in compute()
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
130 if (StressRA && RCI.NumRegs > StressRA) in compute()
131 RCI.NumRegs = StressRA; in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
144 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
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| D | ExecutionDepsFix.cpp | 141 const unsigned NumRegs; member in __anone7243c1d0311::ExeDepsFix
162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} in ExeDepsFix()
268 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
280 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
291 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
323 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
346 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
368 LiveRegs = new LiveReg[NumRegs]; in enterBasicBlock()
371 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
401 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
[all …]
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| D | LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
559 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { in runOnBlock() argument
615 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
625 const unsigned NumRegs = TRI->getNumRegs(); in runOnMachineFunction() local
626 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
627 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
647 runOnBlock(MBB, NumRegs); in runOnMachineFunction()
649 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
650 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
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| D | VirtRegMap.cpp | 71 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow() local
72 Virt2PhysMap.resize(NumRegs); in grow()
73 Virt2StackSlotMap.resize(NumRegs); in grow()
74 Virt2SplitMap.resize(NumRegs); in grow()
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| D | MachineLICM.cpp | 515 unsigned NumRegs = TRI->getNumRegs(); in HoistRegionPostRA() local
516 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. in HoistRegionPostRA()
517 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. in HoistRegionPostRA()
552 BitVector TermRegs(NumRegs); in HoistRegionPostRA()
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| D | StackMaps.cpp | 244 for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) in parseRegisterLiveOutMask() local
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| /external/llvm/lib/Target/R600/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 171 unsigned NumRegs; in printRegOperand() local
175 NumRegs = 1; in printRegOperand()
178 NumRegs = 1; in printRegOperand()
181 NumRegs = 2; in printRegOperand()
184 NumRegs = 2; in printRegOperand()
187 NumRegs = 4; in printRegOperand()
190 NumRegs = 4; in printRegOperand()
193 NumRegs = 3; in printRegOperand()
196 NumRegs = 8; in printRegOperand()
199 NumRegs = 8; in printRegOperand()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 29 unsigned NumRegs; member
36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0), in RCInfo()
40 return makeArrayRef(Order.get(), NumRegs);
87 return get(RC).NumRegs; in getNumAllocatableRegs()
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| D | LiveVariables.h | 181 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
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| D | FastISel.h | 467 void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array variable
258 NumRegs = NR; in InitMCRegisterInfo()
324 assert(RegNo < NumRegs &&
369 return NumRegs; in getNumRegs()
419 assert(RegNo < NumRegs && in getEncodingValue()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 111 uint8_t NumRegs; // D registers loaded or stored member
387 unsigned NumRegs = TableEntry->NumRegs; in ExpandVLD() local
398 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVLD()
400 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVLD()
402 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVLD()
452 unsigned NumRegs = TableEntry->NumRegs; in ExpandVST() local
473 if (NumRegs > 1 && TableEntry->copyAllListRegs) in ExpandVST()
475 if (NumRegs > 2 && TableEntry->copyAllListRegs) in ExpandVST()
477 if (NumRegs > 3 && TableEntry->copyAllListRegs) in ExpandVST()
505 unsigned NumRegs = TableEntry->NumRegs; in ExpandLaneOp() local
[all …]
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| D | Thumb1FrameLowering.cpp | 507 bool NumRegs = false; in restoreCalleeSavedRegisters() local
523 NumRegs = true; in restoreCalleeSavedRegisters()
527 if (NumRegs) in restoreCalleeSavedRegisters()
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| D | ARMLoadStoreOptimizer.cpp | 486 unsigned NumRegs = Regs.size(); in MergeOps() local
487 if (NumRegs <= 1) in MergeOps()
502 for (unsigned I = 0; I < NumRegs; ++I) in MergeOps()
520 } else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) { in MergeOps()
522 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { in MergeOps()
533 if (NumRegs <= 2) in MergeOps()
545 NewBase = Regs[NumRegs-1].first; in MergeOps()
649 UpdateBaseRegUses(MBB, MBBI, dl, Base, NumRegs, Pred, PredReg); in MergeOps()
659 for (unsigned i = 0; i != NumRegs; ++i) in MergeOps()
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| D | ARMBaseInstrInfo.cpp | 3022 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); in getNumMicroOps() local
3023 return (NumRegs / 2) + (NumRegs % 2) + 1; in getNumMicroOps()
3058 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; in getNumMicroOps() local
3060 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. in getNumMicroOps()
3095 if (NumRegs < 4) in getNumMicroOps()
3099 int A8UOps = (NumRegs / 2); in getNumMicroOps()
3100 if (NumRegs % 2) in getNumMicroOps()
3104 int A9UOps = (NumRegs / 2); in getNumMicroOps()
3107 if ((NumRegs % 2) || in getNumMicroOps()
3114 return NumRegs; in getNumMicroOps()
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| D | ARMISelDAGToDAG.cpp | 1653 unsigned NumRegs = NumVecs; in GetVLDSTAlign() local
1655 NumRegs *= 2; in GetVLDSTAlign()
1658 if (Alignment >= 32 && NumRegs == 4) in GetVLDSTAlign()
1660 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) in GetVLDSTAlign()
3365 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag); in SelectInlineAsm() local
3366 if (NumRegs) in SelectInlineAsm()
3383 || NumRegs != 2) in SelectInlineAsm()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1178 unsigned NumRegs = 1; in printVectorList() local
1181 NumRegs = 2; in printVectorList()
1184 NumRegs = 3; in printVectorList()
1187 NumRegs = 4; in printVectorList()
1203 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { in printVectorList()
1205 if (i + 1 != NumRegs) in printVectorList()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 255 unsigned NumRegs = in getCopyFromPartsVector() local
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); in getCopyFromPartsVector()
259 NumParts = NumRegs; // Silence a compiler warning. in getCopyFromPartsVector()
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, in getCopyToPartsVector() local
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); in getCopyToPartsVector()
545 NumParts = NumRegs; // Silence a compiler warning. in getCopyToPartsVector()
625 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); in RegsForValue() local
627 for (unsigned i = 0; i != NumRegs; ++i) in RegsForValue()
630 Reg += NumRegs; in RegsForValue()
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); in getCopyFromRegs() local
[all …]
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| D | FunctionLoweringInfo.cpp | 496 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs() local
497 for (unsigned i = 0; i != NumRegs; ++i) { in CreateRegs()
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| D | FastISel.cpp | 295 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { in updateValueMap() argument
307 for (unsigned i = 0; i < NumRegs; i++) in updateValueMap()
905 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT); in lowerCallTo() local
906 for (unsigned i = 0; i != NumRegs; ++i) { in lowerCallTo()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3575 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs() local
3576 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; in copyByValRegs()
3594 if (!NumRegs) in copyByValRegs()
3601 for (unsigned I = 0; I < NumRegs; ++I) { in copyByValRegs()
3627 unsigned NumRegs = LastReg - FirstReg; in passByValArg() local
3629 if (NumRegs) { in passByValArg()
3631 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); in passByValArg()
3635 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { in passByValArg()
3767 unsigned NumRegs = 0; in HandleByVal() local
3796 Size -= RegSizeInBytes, ++I, ++NumRegs) in HandleByVal()
[all …]
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 860 unsigned NumRegs; member in __anonb19727160511::Cost
870 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0), in Cost()
880 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds in isValid()
882 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds in isValid()
889 return NumRegs == ~0u; in isLoser()
950 ++NumRegs; in RateRegister()
1043 NumRegs = ~0u; in Lose()
1054 return std::tie(NumRegs, AddRecCost, NumIVMuls, NumBaseAdds, ScaleCost, in operator <()
1056 std::tie(Other.NumRegs, Other.AddRecCost, Other.NumIVMuls, in operator <()
1062 OS << NumRegs << " reg" << (NumRegs == 1 ? "" : "s"); in print()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 885 template <unsigned NumRegs> bool isImplicitlyTypedVectorList() const { in isImplicitlyTypedVectorList()
886 return Kind == k_VectorList && VectorList.Count == NumRegs && in isImplicitlyTypedVectorList()
890 template <unsigned NumRegs, unsigned NumElements, char ElementKind>
894 if (VectorList.Count != NumRegs) in isTypedVectorList()
1144 template <unsigned NumRegs>
1149 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands()
1155 template <unsigned NumRegs>
1160 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1504 unsigned NumRegs) { in forwardCopyWillClobberTuple() argument
1507 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
1519 unsigned NumRegs = Indices.size(); in copyPhysRegTuple() local
1521 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple()
1522 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) { in copyPhysRegTuple()
1523 SubReg = NumRegs - 1; in copyPhysRegTuple()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 1541 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; in getRegisterListOpValue() local
1544 Binary |= NumRegs; in getRegisterListOpValue()
1546 Binary |= NumRegs * 2; in getRegisterListOpValue()
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