| /external/llvm/lib/Target/R600/ |
| D | SILoadStoreOptimizer.cpp | 66 unsigned Offset1,
135 unsigned Offset1, in offsetsCanBeCombined() argument
139 if (Offset0 == Offset1) in offsetsCanBeCombined()
143 if ((Offset0 % Size != 0) || (Offset1 % Size != 0)) in offsetsCanBeCombined()
147 unsigned EltOffset1 = Offset1 / Size; in offsetsCanBeCombined()
186 unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local
189 if (offsetsCanBeCombined(Offset0, Offset1, EltSize)) in findMatchingDSInst()
224 unsigned Offset1 in mergeRead2Pair() local
228 unsigned NewOffset1 = Offset1 / EltSize; in mergeRead2Pair()
311 unsigned Offset1 in mergeWrite2Pair() local
[all …]
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| D | AMDGPUInstrInfo.cpp | 213 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
215 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
221 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 118 int64_t Offset1, int64_t Offset2,
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| D | SIInstrInfo.cpp | 79 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); in areLoadsFromSameBasePtr()
136 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
170 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
215 uint8_t Offset1 = Offset1Imm->getImm(); in getLdStBaseRegImmOfs() local
216 assert(Offset1 > Offset0); in getLdStBaseRegImmOfs()
218 if (Offset1 - Offset0 == 1) { in getLdStBaseRegImmOfs()
1037 unsigned BaseReg1, Offset1; in checkInstOffsetsDoNotOverlap() local
1040 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1046 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { in checkInstOffsetsDoNotOverlap()
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| D | AMDGPUISelDAGToDAG.cpp | 92 SDValue &Offset1) const;
861 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
872 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8); in SelectDS64Bit4ByteAligned()
889 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8); in SelectDS64Bit4ByteAligned()
897 Offset1 = CurDAG->getTargetConstant(1, MVT::i8); in SelectDS64Bit4ByteAligned()
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| D | SIInstrInfo.h | 76 int64_t &Offset1,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
190 assert(Offset2 > Offset1 in shouldScheduleLoadsNear()
195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 110 int64_t Offset1, int64_t Offset2,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 225 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
226 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
227 Offset1 == Offset2) in ClusterNeighboringLoads()
231 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
232 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
235 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| D | DAGCombiner.cpp | 8785 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); in CombineToPreIndexedLoadStore() local
8796 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; in CombineToPreIndexedLoadStore()
8797 else CNV = CNV - Offset1; in CombineToPreIndexedLoadStore()
13203 int64_t Offset1, Offset2; in isAlias() local
13207 Base1, Offset1, GV1, CV1); in isAlias()
13213 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
13214 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
13222 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); in isAlias()
13224 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
13225 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
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| D | SelectionDAG.cpp | 6684 int64_t Offset1 = 0; in isConsecutiveLoad() local
6686 bool isGA1 = TLI->isGAPlusOffset(Loc.getNode(), GV1, Offset1); in isConsecutiveLoad()
6689 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 349 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
361 int64_t Offset1, int64_t Offset2,
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| D | X86InstrInfo.cpp | 5640 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
5736 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); in areLoadsFromSameBasePtr()
5745 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
5747 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
5748 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 433 ; CHECK-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
435 ; CHECK-DAG: ldx [%sp+[[Offset1]]], %o3
447 ; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
450 ; CHECK: ld [%fp+[[Offset1]]], %f1
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 207 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
219 int64_t Offset1, int64_t Offset2,
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| D | ARMBaseInstrInfo.cpp | 1528 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1589 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1609 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1614 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
1616 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 823 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
836 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /external/clang/lib/CodeGen/ |
| D | CGVTables.cpp | 892 uint64_t Offset1 = cast<llvm::ConstantInt>( in EmitVTableBitSetEntries() local
898 assert(Offset1 != Offset2); in EmitVTableBitSetEntries()
899 return Offset1 < Offset2; in EmitVTableBitSetEntries()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | MemCpyOptimizer.cpp | 119 int64_t Offset1 = GetOffsetFromIndex(GEP1, Idx, VariableIdxFound, DL); in IsPointerOffset() local
123 Offset = Offset2-Offset1; in IsPointerOffset()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 8124 int Offset1, int Offset2, int Offset4, int Offset8> {
8144 !cast<Operand>("GPR64pi" # Offset1)>;
8147 !cast<Operand>("GPR64pi" # Offset1)>;
8167 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8168 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8946 int64_t Offset1 = 0; in isConsecutiveLSLoc() local
8948 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); in isConsecutiveLSLoc()
8951 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLSLoc()
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