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Searched refs:Op2 (Results 1 – 25 of 56) sorted by relevance

123

/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
[all …]
/external/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h58 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy() argument
75 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
91 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset() argument
105 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcmp() argument
146 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp102 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
118 NewMI->addOperand(Op2); in runOnMachineFunction()
145 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
156 NewMI->addOperand(Op2); in runOnMachineFunction()
187 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
197 NewMI->addOperand(Op2); in runOnMachineFunction()
224 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
238 NewMI->addOperand(Op2); in runOnMachineFunction()
DHexagonPeephole.cpp290 MachineOperand Op2 = MI->getOperand(S2); in runOnMachineFunction() local
291 ChangeOpInto(MI->getOperand(S1), Op2); in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h627 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
633 Ops.push_back(Op2);
880 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
881 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
883 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
885 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
896 SDValue Op1, SDValue Op2);
898 SDValue Op1, SDValue Op2, SDValue Op3);
911 EVT VT2, SDValue Op1, SDValue Op2);
913 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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DISDOpcodes.h849 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
855 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
/external/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp159 MCOperand Op2 = MI.getOperand(2); in getMemoryOpValue() local
160 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
161 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp68 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
109 if (Op2.isImm() && Op3.isImm()) { in printInst()
112 int64_t immr = Op2.getImm(); in printInst()
143 if (Op2.getImm() > Op3.getImm()) { in printInst()
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
161 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
171 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; in printInst()
180 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()) in printInst()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp712 SDValue Op2 = Op.getOperand(2); in ExpandSELECT() local
715 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); in ExpandSELECT()
748 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
755 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
756 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
889 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
917 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
924 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
925 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
DSelectionDAG.cpp319 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation() argument
321 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) in getSetCCOrOperation()
325 unsigned Op = Op1 | Op2; // Combine all of the condition bits. in getSetCCOrOperation()
343 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation() argument
345 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) in getSetCCAndOperation()
350 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
888 SDValue Op1, SDValue Op2, in FindModifiedNodeSlot() argument
893 SDValue Ops[] = { Op1, Op2 }; in FindModifiedNodeSlot()
5397 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { in UpdateNodeOperands() argument
5401 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) in UpdateNodeOperands()
[all …]
DSelectionDAGBuilder.cpp2819 SDValue Op2 = getValue(I.getOperand(1)); in visitFSub() local
2821 Op2.getValueType(), Op2)); in visitFSub()
2830 SDValue Op2 = getValue(I.getOperand(1)); in visitBinary() local
2845 Op1, Op2, nuw, nsw, exact); in visitBinary()
2851 SDValue Op2 = getValue(I.getOperand(1)); in visitShift() local
2854 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType()); in visitShift()
2857 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2859 unsigned Op2Size = Op2.getValueType().getSizeInBits(); in visitShift()
2864 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2870 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) in visitShift()
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DLegalizeIntegerTypes.cpp186 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic1() local
190 Op2, N->getMemOperand(), N->getOrdering(), in PromoteIntRes_Atomic1()
221 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_AtomicCmpSwap() local
224 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other); in PromoteIntRes_AtomicCmpSwap()
227 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(), in PromoteIntRes_AtomicCmpSwap()
944 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntOp_ATOMIC_STORE() local
946 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), in PromoteIntOp_ATOMIC_STORE()
1500 unsigned Op1, Op2; in ExpandShiftWithKnownAmountBit() local
1503 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
1505 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; in ExpandShiftWithKnownAmountBit()
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/external/llvm/lib/Analysis/
DConstantFolding.cpp1602 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { in ConstantFoldScalarCall() local
1603 if (Op2->getType() != Op1->getType()) in ConstantFoldScalarCall()
1606 double Op2V = getValueAsDouble(Op2); in ConstantFoldScalarCall()
1612 APFloat V2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1619 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1625 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1655 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { in ConstantFoldScalarCall() local
1669 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1672 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1675 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
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/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp174 ICToken Op2 = OperandStack.pop_back_val(); in execute() local
181 Val = Op1.second + Op2.second; in execute()
185 Val = Op1.second - Op2.second; in execute()
189 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
191 Val = Op1.second * Op2.second; in execute()
195 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
197 assert (Op2.second != 0 && "Division by zero!"); in execute()
198 Val = Op1.second / Op2.second; in execute()
202 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
204 Val = Op1.second | Op2.second; in execute()
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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp837 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in fromString() local
843 Ops[5].getAsInteger(10, Op2); in fromString()
844 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in fromString()
872 uint32_t Op2 = Bits & 0x7; in toString() local
875 + "_c" + utostr(CRm) + "_" + utostr(Op2); in toString()
/external/llvm/lib/Target/XCore/
DXCoreSelectionDAGInfo.h31 SDValue Op1, SDValue Op2,
/external/llvm/lib/Transforms/Scalar/
DLoopRerollPass.cpp1185 Value *Op2 = RootInst->getOperand(j); in validate() local
1191 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) in validate()
1195 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); in validate()
1197 Op2 = BMI->second; in validate()
1200 if (DRS.Roots[Iter-1] == (Instruction*) Op2) { in validate()
1201 Op2 = DRS.BaseInst; in validate()
1207 if (BaseInst->getOperand(Swapped ? unsigned(!j) : j) != Op2) { in validate()
1214 BaseInst->getOperand(!j) == Op2) { in validate()
DScalarizer.cpp396 Scatterer Op2 = scatter(&SI, SI.getOperand(2)); in visitSelectInst() local
398 assert(Op2.size() == NumElems && "Mismatched select"); in visitSelectInst()
406 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I], in visitSelectInst()
411 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I], in visitSelectInst()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h54 SDValue Op1, SDValue Op2,
/external/llvm/include/llvm/Analysis/
DScalarEvolution.h623 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
628 Ops.push_back(Op2);
641 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
646 Ops.push_back(Op2);
/external/llvm/include/llvm/Transforms/Utils/
DBuildLibCalls.h89 Value *EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name,
/external/llvm/lib/Transforms/Utils/
DBuildLibCalls.cpp299 Value *llvm::EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name, in EmitBinaryFloatFnCall() argument
306 Op1->getType(), Op2->getType(), nullptr); in EmitBinaryFloatFnCall()
307 CallInst *CI = B.CreateCall2(Callee, Op1, Op2, Name); in EmitBinaryFloatFnCall()
/external/llvm/lib/Target/R600/
DR600InstrFormats.td24 bit Op2 = 0;
53 let TSFlags{11} = Op2;
/external/llvm/lib/AsmParser/
DLLParser.cpp4605 BasicBlock *Op1, *Op2; in ParseBr() local
4619 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) in ParseBr()
4622 Inst = BranchInst::Create(Op1, Op2, Op0); in ParseBr()
4944 Value *Op0, *Op1, *Op2; in ParseSelect() local
4949 ParseTypeAndValue(Op2, PFS)) in ParseSelect()
4952 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) in ParseSelect()
4955 Inst = SelectInst::Create(Op0, Op1, Op2); in ParseSelect()
4998 Value *Op0, *Op1, *Op2; in ParseInsertElement() local
5003 ParseTypeAndValue(Op2, PFS)) in ParseInsertElement()
5006 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) in ParseInsertElement()
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/external/llvm/include/llvm/IR/
DPatternMatch.h1246 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
1247 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));

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