| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 73 unsigned Opc1, Opc2; in processBlock() local
83 Opc1 = PPC::ADDItlsgdL; in processBlock()
87 Opc1 = PPC::ADDItlsldL; in processBlock()
91 Opc1 = PPC::ADDItlsgdL32; in processBlock()
95 Opc1 = PPC::ADDItlsldL32; in processBlock()
101 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) in processBlock()
|
| D | PPCISelDAGToDAG.cpp | 2911 unsigned Opc1, Opc2, Opc3; in Select() local
2915 Opc1 = PPC::VSPLTISB; in Select()
2920 Opc1 = PPC::VSPLTISH; in Select()
2926 Opc1 = PPC::VSPLTISW; in Select()
2940 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
2952 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
2954 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
2966 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
2968 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
|
| D | Mips16ISelLowering.cpp | 583 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, in emitSelT16() argument
621 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
647 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
686 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
|
| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 54 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
84 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
90 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
116 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
141 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
151 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
280 unsigned Opc1 = SecondLdSt->getOpcode(); in shouldClusterLoads() local
[all …]
|
| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 635 template <typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2>
643 if (V->getValueID() == Value::InstructionVal + Opc1 || in match()
649 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && in match()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 324 unsigned Opc1 = I->getOpcode(); in RemoveBranch() local
325 switch (Opc1) { in RemoveBranch()
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 33 unsigned Opc1; member
|
| D | X86InstrInfo.cpp | 5643 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
5645 switch (Opc1) { in areLoadsFromSameBasePtr()
5751 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
5753 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
5756 switch (Opc1) { in shouldScheduleLoadsNear()
|
| D | X86ISelLowering.cpp | 14762 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
14785 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
14835 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
15308 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0); in LowerINTRINSIC_W_CHAIN()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 375 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
|