Home
last modified time | relevance | path

Searched refs:Q5 (Results 1 – 25 of 39) sorted by relevance

12

/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s193 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
205 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
219 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
223 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
260 VADDW.U8 Q8,Q5,D28 @//Q2 - HAS Y + R
264 VADDW.U8 Q11,Q5,D29 @//Q11 - HAS Y + R
324 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
336 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
350 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
354 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td60 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
62 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
64 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
67 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
69 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
96 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
98 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
100 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
103 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
105 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
DAArch64CallingConvention.h41 AArch64::Q3, AArch64::Q4, AArch64::Q5,
DAArch64PBQPRegAlloc.cpp82 case AArch64::Q5: in isOdd()
/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class1.s132 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
135 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
147 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
152 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
189 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
226 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
227 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
254 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
277 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
278 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
Dihevc_sao_edge_offset_class1_chroma.s137 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
140 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
152 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
157 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
197 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
239 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
240 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
272 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
295 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
296 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
Dihevc_sao_edge_offset_class2.s248 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
252 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
293 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
297 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
299 VADD.I8 Q12,Q12,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
305 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
375 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
385 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
394 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
398 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
Dihevc_sao_edge_offset_class3.s263 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
273 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
308 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
310 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
313 VADD.I8 Q9,Q9,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
315 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
410 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
419 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
423 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
425 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
Dihevc_sao_edge_offset_class2_chroma.s340 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
344 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
732 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
733 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
877 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
878 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
Dihevc_sao_edge_offset_class3_chroma.s330 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
334 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
722 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
726 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
903 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
905 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
/external/fdlibm/
Ds_expm1.c127 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
187 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
/external/libavc/common/arm/
Dih264_deblk_chroma_a9.s102 vaddl.u8 q5, d7, d1 @Q4,Q5 = q0 + p1
107 vmlal.u8 q5, d3, d31 @Q5,Q4 = (X2(q1U) + q0U + p1U)
122 vrshrn.u16 d11, q14, #2 @Q5 = (X2(p1U) + p0U + q1U + 2) >> 2
185 vdup.8 q12, r3 @Q5 = beta
288 vsubl.u8 q4, d0, d4 @Q5,Q4 = (q0 - p0)
290 vshl.i16 q5, q5, #2 @Q5 = (q0 - p0)<<2
300 vadd.i16 q5, q5, q3 @Q5,Q4 = [ (q0 - p0)<<2 ] + (p1 - q1)
392 vdup.8 q12, r3 @Q5 = beta
714 vaddl.u8 q5, d7, d1 @Q4,Q5 = q0 + p1
719 vmlal.u8 q5, d3, d31 @Q5,Q4 = (X2(q1U) + q0U + p1U)
[all …]
Dih264_deblk_luma_a9.s148 vaddl.u8 q5, d16, d10 @Q14,Q5 = p2 + (p0+q0+1)>>1
155 vsub.i16 q14, q14, q13 @Q14,Q5 = [p2 + (p0+q0+1)>>1] - (p1<<1)
241 vld1.8 {d10, d11}, [r14] @load p1 to Q5
Dih264_iquant_itrans_recon_a9.s603 vswp d5, d12 @ Q4/Q5 = Row order x4/x5
665 vsub.s16 q5, q3, q9 @ Q5 = z5
684 vsub.s16 q5, q2, q6 @ Q5 = x5
719 vswp d5, d12 @ Q4/Q5 = Row order x4/x5
787 vsub.s16 q5, q3, q9 @ Q5 = z5
805 vsub.s16 q5, q2, q6 @ Q5 = x5
Dih264_ihadamard_scaling_a9.s127 vswp d7, d10 @Q3 = x5, Q5 = x7
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/fr-FR/
Dfr-FR_nk0_kdt_mgc3.pkb69 Q5
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/it-IT/
Dit-IT_cm0_kdt_lfz3.pkb130 …4[�`�.����62�=�EB����ۻ��T,SE>J7Kt��*�yt'ev����!�8b�;�į���lw��3Q5>2��HS���İa�}�`sL9I…
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp102 SP::Q5, SP::Q13, ~0U, ~0U,
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td171 def Q5 : Rq<20, "F20", [D10, D11]>;
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1132 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
1133 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
/external/llvm/lib/Target/ARM/
DARMCallingConv.td98 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/es-ES/
Des-ES_kpr.pkb1720 …���������������������������������������������������������I5��E�D�����Q5��f�e�����W5��k�j����…
/external/valgrind/memcheck/
Dmc_machine.c999 if (o >= GOF(Q5) && o+sz <= GOF(Q5) +SZB(Q5)) return GOF(Q5); in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp123 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp249 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
429 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,

12