| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrSPE.td | 18 bits<5> RA;
24 let Inst{11-15} = RA;
37 bits<5> RA;
44 let Inst{11-15} = RA;
111 def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
112 "evmra $RT, $RA", IIC_VecFP> {
116 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
117 "brinc $RT, $RA, $RB", IIC_VecFP>;
118 def EVABS : EVXForm_2<520, (outs gprc:$RT), (ins gprc:$RA),
119 "evabs $RT, $RA", IIC_VecFP>;
[all …]
|
| D | PPCInstrHTM.td | 109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
124 def : Pat<(int_ppc_treclaim i32:$RA),
125 (TRECLAIM $RA)>;
|
| /external/valgrind/none/tests/ppc64/ |
| D | opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) argument
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) argument
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES) argument
54 #define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH)) argument
|
| /external/valgrind/none/tests/ppc32/ |
| D | opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) argument
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) argument
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES) argument
54 #define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH)) argument
|
| /external/clang/test/Layout/ |
| D | ms-x86-alias-avoidance-padding.cpp | 301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
|
| D | ms-x86-pack-and-align.cpp | 430 struct RA {}; struct
441 struct __declspec(align(8)) RB2 : virtual RA {
445 struct __declspec(align(8)) RB3 : virtual RA {
|
| /external/tcpdump/tests/ |
| D | ieee802.11_exthdr.out | 2 …s 2412 MHz 11b -19dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
5 …s 2412 MHz 11b -18dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
8 …s 2412 MHz 11b -46dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
11 …s 2412 MHz 11b -57dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
14 …s 2412 MHz 11b -73dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
17 …s 2412 MHz 11b -74dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
20 …s 2412 MHz 11b -17dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
23 …s 2412 MHz 11b -18dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
|
| /external/llvm/test/CodeGen/X86/ |
| D | scheduler-backtracking.ll | 1 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-ilp | FileCheck %s
2 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-hybrid | FileCheck %s
3 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=source | FileCheck %s
4 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-burr | FileCheck %s
5 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=linearize | FileCheck %s
|
| D | break-anti-dependencies.ll | 2 ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
4 ; RUN: llc < %s -march=x86-64 -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=lis…
7 ; RUN: llc < %s -march=x86-64 -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical > %t
|
| D | 2012-05-17-TwoAddressBug.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-macosx -pre-RA-sched=source | FileCheck %s
5 ; because of poor pre-RA schedule. That will be fixed by MI scheduler.
|
| D | pre-ra-sched.ll | 1 …< %s -verify-machineinstrs -mtriple=x86_64-apple-macosx -pre-RA-sched=ilp -debug-only=pre-RA-sched…
6 ; rdar:13279013: pre-RA-sched should not check all interferences and
|
| /external/clang/test/CodeGenCXX/ |
| D | devirtualize-virtual-function-calls-final.cpp | 179 struct RA { struct
187 struct RC final : public RA {
212 return static_cast<RA*>(x)->f(); in f()
225 return -static_cast<RA&>(*x); in fop()
|
| /external/icu/icu4c/source/data/translit/ |
| D | InterIndic_Gurmukhi.txt | 24 \uE00B→ਰਿ; # REMAP (indicExceptions.txt): \u0A0B→ਰਿ = LETTER VOCALIC R→LETTER RA.VOWEL SIGN I
61 \uE030→ਰ; # LETTER RA
62 \uE031→ਰ\u0A3C; # FALLBACK LETTER RA+NUKTA
97 \uE058→ਕ\u0A3C; # FALLBACK RA+ NUKTA
105 \uE060→ਰਿ; # REMAP (indicExceptions.txt): \u0A60→ਰਿ = LETTER VOCALIC RR→LETTER RA.VOWEL SIGN I
122 \uE071→ਰ; # LETTER RA WITH MIDDLE DIAGONAL
123 \uE072→ਰ; # LETTER RA WITH LOWER DIAGONAL
|
| D | InterIndic_Tamil.txt | 20 \uE00B→ரி; # REMAP (indicExceptions.txt): \u0B8B→ரி = LETTER VOCALIC R→LETTER RA.VOWEL SIGN I
59 \uE030→ர; # LETTER RA
77 …AP (indicExceptions.txt): \u0BC3→\u0BCDரி = VOWEL SIGN VOCALIC R→SIGN VIRAMA.LETTER RA.VOWEL SIGN I
78 …P (indicExceptions.txt): \u0BC4→\u0BCDரி = VOWEL SIGN VOCALIC RR→SIGN VIRAMA.LETTER RA.VOWEL SIGN I
104 \uE060→ரி; # REMAP (indicExceptions.txt): \u0BE0→ரி = LETTER VOCALIC RR→LETTER RA.VOWEL SIGN I
121 \uE071→\u0BC0; # LETTER RA WITH MIDDLE DIAGONAL
122 \uE072→\u0BC0; # LETTER RA WITH LOWER DIAGONAL
|
| D | InterIndic_Bengali.txt | 57 \uE030→র; # LETTER RA
58 \uE031→র\u09BC; # FALLBACK to RA
118 \uE071→ৰ; # LETTER RA WITH MIDDLE DIAGONAL
119 \uE072→ৱ; # LETTER RA WITH LOWER DIAGONAL
|
| D | InterIndic_Devanagari.txt | 74 \uE030 → र; # LETTER RA
75 \uE031 → ऱ; # LETTER RRA (Eyelash RA for Southern scripts)
132 \uE071→र; # LETTER RA WITH MIDDLE DIAGONAL
133 \uE072→र; # LETTER RA WITH LOWER DIAGONAL
|
| D | Bengali_InterIndic.txt | 53 র→\uE030; # LETTER RA
89 ৰ→\uE071; # Bengali-InterIndic: LETTER RA WITH MIDDLE DIAGONAL
90 ৱ→\uE072; # Bengali-InterIndic: LETTER RA WITH LOWER DIAGONAL
|
| /external/llvm/test/CodeGen/Generic/ |
| D | 2006-07-03-schedulers.ll | 1 ; RUN: llc < %s -pre-RA-sched=default
2 ; RUN: llc < %s -pre-RA-sched=list-burr
3 ; RUN: llc < %s -pre-RA-sched=fast
|
| /external/llvm/utils/TableGen/ |
| D | FixedLenDecoderEmitter.cpp | 461 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
1360 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, in reportRegion() argument
1362 if (RA == ATTR_MIXED && AllowMixed) in reportRegion()
1364 else if (RA == ATTR_ALL_SET && !AllowMixed) in reportRegion()
1482 bitAttr_t RA = ATTR_NONE; in filterProcessor() local
1490 switch (RA) { in filterProcessor()
1497 RA = ATTR_ALL_SET; in filterProcessor()
1503 RA = ATTR_MIXED; in filterProcessor()
1512 reportRegion(RA, StartBit, BitIndex, AllowMixed); in filterProcessor()
1513 RA = ATTR_NONE; in filterProcessor()
[all …]
|
| /external/llvm/lib/Transforms/IPO/ |
| D | DeadArgumentElimination.cpp | 153 void MarkValue(const RetOrArg &RA, Liveness L,
155 void MarkLive(const RetOrArg &RA);
157 void PropagateLiveness(const RetOrArg &RA);
667 void DAE::MarkValue(const RetOrArg &RA, Liveness L, in MarkValue() argument
670 case Live: MarkLive(RA); break; in MarkValue()
677 Uses.insert(std::make_pair(*UI, RA)); in MarkValue()
702 void DAE::MarkLive(const RetOrArg &RA) { in MarkLive() argument
703 if (LiveFunctions.count(RA.F)) in MarkLive()
706 if (!LiveValues.insert(RA).second) in MarkLive()
709 DEBUG(dbgs() << "DAE - Marking " << RA.getDescription() << " live\n"); in MarkLive()
[all …]
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 85 def RA : AMDILReg<998, "r998">, DwarfRegNum<[998]>;
88 …(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, …
96 …(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, …
104 …(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, …
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | postra-mi-sched.ll | 4 ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
5 ; post-RA MI scheduler will clean this up.
|
| /external/llvm/test/Transforms/LoopStrengthReduce/AArch64/ |
| D | lsr-memcpy.ll | 1 ; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck …
5 ; Remove the -pre-RA-sched=list-hybrid option after fixing:
|
| /external/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 44 const MCReadAdvanceEntry *RA, in InitMCSubtargetInfo() argument
55 ReadAdvanceTable = RA; in InitMCSubtargetInfo()
|
| /external/icu/icu4c/source/test/testdata/ |
| D | translit_rules.txt | 54 \uE030>\u09B0; # LETTER RA
55 \uE031>\u09B0\u09BC; # FALLBACK to RA
115 \ue071>\u09F0; # LETTER RA WITH MIDDLE DIAGONAL
116 \ue072>\u09F1; # LETTER RA WITH LOWER DIAGONAL
|