| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 361 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
367 std::reverse(RVLocs.begin(), RVLocs.end()); in AnalyzeReturnValues()
532 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
539 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
543 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
549 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
550 CCValAssign &VA = RVLocs[i]; in LowerReturn()
725 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
726 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
729 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 395 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
399 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
414 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
415 CCValAssign &VA = RVLocs[i]; in LowerReturn()
443 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
444 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCallResult()
455 for (auto &Val : RVLocs) { in LowerCallResult()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1072 const SmallVectorImpl<CCValAssign> &RVLocs, in LowerCallResult() argument
1077 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
1078 const CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1138 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1140 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCCCCallTo()
1243 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1452 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1453 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1474 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1477 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2036 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2037 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); in FinishCall()
2041 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2044 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2049 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2050 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2052 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2053 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2058 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
2059 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
[all …]
|
| D | ARMISelLowering.cpp | 1336 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1337 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1344 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1345 CCValAssign VA = RVLocs[i]; in LowerCallResult()
1363 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1377 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1381 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2135 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2136 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
2181 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 190 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
205 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_32()
206 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
250 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
253 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_64()
267 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_64()
268 CCValAssign &VA = RVLocs[i]; in LowerReturn_64()
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
937 SmallVector<CCValAssign, 16> RVLocs; in LowerCall_32() local
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1080 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1081 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1085 if (RVLocs.size() != 1) in finishCall()
1088 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
1096 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1097 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
|
| D | MipsISelLowering.cpp | 2775 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2776 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2781 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2782 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
2785 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2786 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
3050 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3051 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
3072 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3076 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1370 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1371 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1373 CCValAssign &VA = RVLocs[0]; in finishCall()
1374 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1459 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
1460 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); in fastLowerCall()
1462 if (RVLocs.size() > 1) in fastLowerCall()
|
| D | PPCISelLowering.cpp | 4099 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
4100 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
4105 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
4106 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
5533 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
5534 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
5545 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
5546 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
5554 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
5555 CCValAssign &VA = RVLocs[i]; in LowerReturn()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 335 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
338 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
348 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
349 CCValAssign &VA = RVLocs[i]; in LowerReturn()
386 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
388 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
394 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
396 RVLocs[i].getLocReg(), in LowerCallResult()
397 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3129 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
3130 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, in fastLowerCall()
3136 for (unsigned i = 0; i != RVLocs.size(); ++i) { in fastLowerCall()
3137 CCValAssign &VA = RVLocs[i]; in fastLowerCall()
3178 CLI.NumResultRegs = RVLocs.size(); in fastLowerCall()
|
| D | X86ISelLowering.cpp | 1861 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1862 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1880 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1881 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
1892 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
1893 CCValAssign &VA = RVLocs[i]; in LowerReturn()
2057 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2059 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2064 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
2065 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3028 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
3029 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
3033 if (RVLocs.size() != 1) in finishCall()
3037 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3046 .addReg(RVLocs[0].getLocReg()); in finishCall()
3047 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
|
| D | AArch64ISelLowering.cpp | 2331 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2332 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2337 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2338 CCValAssign VA = RVLocs[i]; in LowerCallResult()
2899 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2900 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
2913 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
2914 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
2921 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); in LowerReturn()
2923 CCValAssign &VA = RVLocs[i]; in LowerReturn()
|