| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 142 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
145 MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF)); in hasFP()
258 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( in emitPrologue() local
392 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
393 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP, in emitPrologue()
400 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
469 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); in emitPrologue()
477 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true); in emitPrologue()
537 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( in emitEpilogue() local
599 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); in emitEpilogue()
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| D | AArch64CleanupLocalDynamicTLSPass.cpp | 116 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in setRegister() local
117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 76 const MipsRegisterInfo &RegInfo; member in __anon82167c930111::ExpandPseudo
84 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
155 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
192 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
193 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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| D | MipsISelLowering.cpp | 1031 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinary() local
1062 unsigned StoreVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1063 unsigned AndRes = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1064 unsigned Success = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1130 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitSignExtendToI32InReg() local
1132 unsigned ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg()
1150 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinaryPartword() local
1159 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1160 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1161 unsigned Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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| D | Mips16ISelDAGToDAG.cpp | 74 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
80 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
81 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
82 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| D | MipsSEISelLowering.cpp | 2747 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
2776 unsigned VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2782 unsigned VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2812 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
2843 unsigned RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
2849 unsigned RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
2875 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
2886 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
2893 unsigned Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
2920 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
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| D | MipsSERegisterInfo.cpp | 173 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
174 unsigned Reg = RegInfo.createVirtualRegister(RC); in eliminateFI()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 56 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
92 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
103 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
104 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
117 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
265 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
287 if (RegInfo->needsStackRealignment(MF)) in emitPrologue()
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| D | ARMFrameLowering.cpp | 50 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
60 RegInfo->needsStackRealignment(MF) || in hasFP()
290 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
300 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
634 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { in emitPrologue()
664 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
667 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
672 RegInfo->getBaseRegister()) in emitPrologue()
739 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in emitEpilogue() local
748 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 77 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
80 RegInfo->needsStackRealignment(MF) || in hasFP()
472 const X86RegisterInfo *RegInfo = STI.getRegisterInfo(); in calculateMaxStackAlign() local
473 unsigned SlotSize = RegInfo->getSlotSize(); in calculateMaxStackAlign()
574 const X86RegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
591 unsigned SlotSize = RegInfo->getSlotSize(); in emitPrologue()
592 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
597 unsigned StackPtr = RegInfo->getStackRegister(); in emitPrologue()
598 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
626 !RegInfo->needsStackRealignment(MF) && in emitPrologue()
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| D | X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
22 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF); in setRestoreBasePointer()
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| D | X86CallFrameOptimization.cpp | 246 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>( in collectCallInfo() local
248 unsigned StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
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| /external/llvm/lib/CodeGen/ |
| D | MachineFunction.cpp | 60 RegInfo = new (Allocator) MachineRegisterInfo(this); in MachineFunction()
62 RegInfo = nullptr; in MachineFunction()
96 if (RegInfo) { in ~MachineFunction()
97 RegInfo->~MachineRegisterInfo(); in ~MachineFunction()
98 Allocator.Deallocate(RegInfo); in ~MachineFunction()
336 if (RegInfo) { in print()
337 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); in print()
338 if (!RegInfo->tracksLiveness()) in print()
355 if (RegInfo && !RegInfo->livein_empty()) { in print()
358 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { in print()
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| D | MachineInstr.cpp | 150 MachineRegisterInfo *RegInfo = nullptr; in ChangeToRegister() local
154 RegInfo = &MF->getRegInfo(); in ChangeToRegister()
158 if (RegInfo && WasReg) in ChangeToRegister()
159 RegInfo->removeRegOperandFromUseList(this); in ChangeToRegister()
181 if (RegInfo) in ChangeToRegister()
182 RegInfo->addRegOperandToUseList(this); in ChangeToRegister()
1326 const TargetRegisterInfo &RegInfo) { in substituteRegister() argument
1329 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1333 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1339 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | PrologEpilogInserter.cpp | 291 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); in calculateCalleeSavedRegisters() local
296 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F); in calculateCalleeSavedRegisters()
320 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { in calculateCalleeSavedRegisters()
335 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters()
338 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { in calculateCalleeSavedRegisters()
567 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
570 RegInfo->useFPForScavengingIndex(Fn) && in calculateFrameObjectOffsets()
571 !RegInfo->needsStackRealignment(Fn)); in calculateFrameObjectOffsets()
699 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| D | GCRootLowering.cpp | 341 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() local
343 RegInfo->needsStackRealignment(MF); in runOnMachineFunction()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo; variable
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
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| D | NVPTXPrologEpilogPass.cpp | 113 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
213 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 437 const PPCRegisterInfo *RegInfo = in determineFrameLayout() local
446 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
455 !RegInfo->hasBasePointer(MF)) { // No special alignment. in determineFrameLayout()
524 const PPCRegisterInfo *RegInfo = in replaceFPWithRealFP() local
526 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
527 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
564 const PPCRegisterInfo *RegInfo = in emitPrologue() local
609 bool HasBP = RegInfo->hasBasePointer(MF); in emitPrologue()
612 unsigned BPReg = RegInfo->getBaseRegister(MF); in emitPrologue()
923 const PPCRegisterInfo *RegInfo = in emitEpilogue() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZLDCleanup.cpp | 132 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in SetRegister() local
133 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass); in SetRegister()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 501 const MCRegisterInfo *RegInfo; member
530 const MCRegisterInfo *RegInfo, in CreateReg() argument
535 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
549 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
557 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPRMM16Reg()
565 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR64Reg()
575 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) in getAFGR64Reg()
583 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) in getFGR64Reg()
591 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) in getFGR32Reg()
599 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID) in getFGRH32Reg()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 1026 const TargetRegisterInfo &RegInfo);
1033 const TargetRegisterInfo *RegInfo,
1038 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1044 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1058 const TargetRegisterInfo *RegInfo = nullptr);
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| D | MachineFunction.h | 94 MachineRegisterInfo *RegInfo;
188 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
189 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| D | FunctionLoweringInfo.h | 58 MachineRegisterInfo *RegInfo; variable
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 654 const MCRegisterInfo *RegInfo = Context.getRegisterInfo(); in emitFrame() local
657 FrameReg = RegInfo->getEncodingValue(StackReg); in emitFrame()
659 ReturnReg = RegInfo->getEncodingValue(ReturnReg_); in emitFrame()
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