| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4222 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4225 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4230 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4231 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4252 TD->getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4262 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4263 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4308 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4314 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes); in ReplaceLoadVector()
4337 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1388 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1394 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1400 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1682 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
1688 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
1694 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
2879 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
2883 ResVT, WideSETCC, DAG.getConstant(0, in WidenVecOp_SETCC()
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| D | LegalizeIntegerTypes.cpp | 173 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
175 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
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| D | DAGCombiner.cpp | 9379 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
9380 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
9383 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
9397 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
9403 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7896 EVT ResVT = N->getValueType(0); in performExtendCombine() local
7897 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
7904 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
7922 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
7925 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
7938 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
8619 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
8623 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
8632 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
8642 EVT ResVT = N->getValueType(0); in performSelectCombine() local
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| D | AArch64InstrInfo.td | 3575 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3578 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3582 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3595 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3597 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3601 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 828 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
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| D | X86FastISel.cpp | 3164 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3165 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3166 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3171 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
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| D | X86ISelLowering.cpp | 3773 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, in isExtractSubvectorCheap() argument
3775 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
3778 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
5951 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
5953 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
5954 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
5958 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
5959 if (ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
5960 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
5963 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(), in LowerAVXCONCAT_VECTORS()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5774 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
5791 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
5794 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
5803 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
5811 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
5824 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
5827 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
5834 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
5840 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
5846 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1642 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const { in isExtractSubvectorCheap() argument
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2144 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2146 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2162 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
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