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Searched refs:SETNE (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td20 IntRegs:$fval, SETNE)),
80 // and similarly for SETNE
83 IntRegs:$fval, SETNE)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp135 case ISD::SETNE: in softenSetCCOperands()
1254 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1259 Cond = ISD::SETNE; in SimplifySetCC()
1288 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1297 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1422 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
1439 case ISD::SETNE: in SimplifySetCC()
1461 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1470 return DAG.getConstant(Cond == ISD::SETNE, VT); in SimplifySetCC()
1491 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp523 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
698 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
738 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); in PromoteIntRes_XMULO()
743 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
898 case ISD::SETNE: { in PromoteSetCCOperands()
1813 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1843 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2077 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2080 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2341 ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
DLegalizeDAG.cpp1737 case ISD::SETNE: in LegalizeSetCCCondCode()
1740 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ; in LegalizeSetCCCondCode()
2536 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); in ExpandLegalINT_TO_FP()
3647 ISD::SETEQ : ISD::SETNE); in ExpandNode()
3650 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandNode()
3748 ISD::SETNE); in ExpandNode()
3751 DAG.getConstant(0, VT), ISD::SETNE); in ExpandNode()
3778 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
3830 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3942 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
[all …]
DSelectionDAGDumper.cpp326 case ISD::SETNE: return "setne"; in getOperationName()
DLegalizeFloatTypes.cpp759 CCCode = ISD::SETNE; in SoftenFloatOp_BR_CC()
798 CCCode = ISD::SETNE; in SoftenFloatOp_SELECT_CC()
1440 CCCode = ISD::SETNE; in ExpandFloatOp_BR_CC()
1533 CCCode = ISD::SETNE; in ExpandFloatOp_SELECT_CC()
/external/mesa3d/src/mesa/x86/
Dcommon_x86_asm.S66 SETNE (AL)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h804 SETNE, // 1 X 1 1 0 True if not equal enumerator
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp712 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
713 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
714 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
727 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
728 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
729 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
DAnalysis.cpp186 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
201 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h511 X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
551 X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
584 X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
593 X86_INTRINSIC_DATA(sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE),
DX86InstrCMovSetCC.td101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td47 case ISD::SETNE: return true;}}}]
DSIISelLowering.cpp428 && CCOp == ISD::SETNE) { in PerformDAGCombine()
DR600ISelLowering.cpp455 case ISD::SETNE: in LowerSELECT_CC()
DR600Instructions.td293 0xB, "SETNE",
429 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp196 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); in ARMTargetLowering()
197 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); in ARMTargetLowering()
198 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); in ARMTargetLowering()
199 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); in ARMTargetLowering()
200 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); in ARMTargetLowering()
201 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); in ARMTargetLowering()
202 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); in ARMTargetLowering()
215 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); in ARMTargetLowering()
216 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); in ARMTargetLowering()
217 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); in ARMTargetLowering()
[all …]
/external/llvm/lib/Target/R600/
DAMDGPUInstructions.td76 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
DR600ISelLowering.cpp1085 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1216 case ISD::SETNE: in LowerSELECT_CC()
1254 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1982 case ISD::SETNE: return LHS; in PerformDAGCombine()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1938 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
1979 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2040 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
2076 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
2110 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2154 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2221 case ISD::SETNE: { in SelectSETCC()
2254 case ISD::SETNE: { in SelectSETCC()
2664 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
DPPCInstrInfo.td2814 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2885 defm : ExtSetCCPat<SETNE,
2994 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2996 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2999 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3022 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3062 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3064 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3067 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3090 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
[all …]
DPPCInstrQPX.td1035 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETNE),
1082 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETNE),
1127 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETNE)),
1140 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETNE)),
1153 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETNE)),
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1363 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1369 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1376 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1382 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp609 case ISD::SETNE: in EmitInstrWithCustomInserter()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1329 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1348 case ISD::SETNE: in FPCondCCodeToFCC()
1744 CC == ISD::SETNE && in LookThroughSetCC()
2754 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2757 ISD::SETNE); in LowerUMULO_SMULO()

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