| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 788 SETO, // 0 1 1 1 True if ordered (no nans) enumerator
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 170 case FCmpInst::FCMP_ORD: return ISD::SETO; in getFCmpCondCode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 312 case ISD::SETO: return "seto"; in getOperationName()
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| D | TargetLowering.cpp | 164 case ISD::SETO: in softenSetCCOperands()
1764 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
1830 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1698 case ISD::SETO: in LegalizeSetCCCondCode()
1724 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; in LegalizeSetCCCondCode()
1752 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { in LegalizeSetCCCondCode()
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| D | SelectionDAG.cpp | 1854 case ISD::SETO: in FoldSetCC()
1914 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); in FoldSetCC()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 100 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
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| D | SIISelLowering.cpp | 1447 if (LCC == ISD::SETO) { in performAndCombine()
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| D | R600ISelLowering.cpp | 46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 1096 case ISD::SETO: in CombineFMinMaxLegacy()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 540 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
887 (setcc node:$lhs, node:$rhs, SETO)>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1001 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETO),
1048 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETO),
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| D | PPCISelDAGToDAG.cpp | 2049 case ISD::SETO: return PPC::PRED_NU; in getPredicateForSetCC()
2077 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO in getCRIdxForSetCC()
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| D | PPCInstrInfo.td | 3121 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3152 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1582 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in HexagonTargetLowering()
1585 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in HexagonTargetLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 1225 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 637 #define SETO(a) CHOICE(seto a, seto a, seto a) macro
1358 #define SETO(a) seto a macro
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 1093 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \ in CCMaskForCondCode()
1107 case ISD::SETO: return SystemZ::CCMASK_CMP_O; in CCMaskForCondCode()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 964 (setcc node:$lhs, node:$rhs, SETO)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 181 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
182 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
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| D | MipsSEISelLowering.cpp | 1802 Op->getOperand(2), ISD::SETO); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 507 case ISD::SETO: return Mips::FCOND_OR; in condCodeToFCC()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1363 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1248 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
3417 if (CC == ISD::SETO) { in checkVSELConstraints()
4389 case ISD::SETO: in LowerVSETCC()
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