| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 790 SETUEQ, // 1 0 0 1 True if unordered or equal enumerator
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 172 case FCmpInst::FCMP_UEQ: return ISD::SETUEQ; in getFCmpCondCode()
185 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 39 case ISD::SETOEQ: case ISD::SETUEQ:
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| D | R600ISelLowering.cpp | 449 case ISD::SETUEQ: in LowerSELECT_CC()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 107 def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
136 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
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| D | R600ISelLowering.cpp | 53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 1089 case ISD::SETUEQ: in CombineFMinMaxLegacy()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 314 case ISD::SETUEQ: return "setue"; in getOperationName()
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| D | TargetLowering.cpp | 193 case ISD::SETUEQ: in softenSetCCOperands()
1778 if (Cond == ISD::SETUEQ && in SimplifySetCC()
1791 if (Cond == ISD::SETUEQ && in SimplifySetCC()
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| D | SelectionDAG.cpp | 358 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
1856 case ISD::SETUEQ: in FoldSetCC()
1916 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1714 case ISD::SETUEQ: in LegalizeSetCCCondCode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2031 case ISD::SETUEQ: in getPredicateForSetCC()
2078 case ISD::SETUEQ: in getCRIdxForSetCC()
2155 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
2163 case ISD::SETUEQ: in getVCmpInst()
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| D | PPCInstrQPX.td | 1004 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUEQ),
1051 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUEQ),
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| D | PPCISelLowering.cpp | 343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
538 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
568 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
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| D | PPCInstrInfo.td | 2817 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 541 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
891 (setcc node:$lhs, node:$rhs, SETUEQ)>;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1430 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal); in HexagonTargetLowering()
1431 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal); in HexagonTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 968 (setcc node:$lhs, node:$rhs, SETUEQ)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 185 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
186 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
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| D | MipsSEISelLowering.cpp | 1806 Op->getOperand(2), ISD::SETUEQ); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 510 case ISD::SETUEQ: return Mips::FCOND_UEQ; in condCodeToFCC()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1365 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1057 case ISD::SETUEQ: in changeFPCCToAArch64CC()
1102 case ISD::SETUEQ: in changeVectorFPCCToAArch64CC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1250 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; in FPCCToARMCC()
4379 case ISD::SETUEQ: Invert = true; // Fallthrough in LowerVSETCC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3696 case ISD::SETUEQ: in TranslateX86CC()
12948 case ISD::SETUEQ: in translateX86FSETCC()
13083 if (SetCCOpcode == ISD::SETUEQ) { in LowerVSETCC()
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