| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 194 unsigned ShiftAmount; member
336 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
670 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1583 unsigned ShiftAmount, in CreateShiftedImm() argument
1588 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2154 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2160 ShiftAmount = 12; in tryParseAddSubImm()
2164 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
2191 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseAddSubImm() local
2193 if (ShiftAmount < 0) { in tryParseAddSubImm()
[all …]
|
| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2301 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; in SimplifyICmpInst() local
2302 Lower = CI2->getValue().shl(ShiftAmount); in SimplifyICmpInst()
2306 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; in SimplifyICmpInst() local
2308 Upper = CI2->getValue().shl(ShiftAmount) + 1; in SimplifyICmpInst()
2317 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2319 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2320 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
2331 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2333 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2337 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 649 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { in Is_PostInc_S4_Offset() argument
656 if (ShiftAmount > 0) { in Is_PostInc_S4_Offset()
657 m = v % ShiftAmount; in Is_PostInc_S4_Offset()
658 v = v >> ShiftAmount; in Is_PostInc_S4_Offset()
692 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts() local
693 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { in getPostIndexedAddressParts()
1097 SDValue ShiftAmount = DAG.getConstant(16, MVT::i32); in LowerLOAD() local
1098 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); in LowerLOAD()
1119 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount); in LowerLOAD()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 764 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
771 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
775 ShiftAmount -= 1; in LowerShifts()
778 while (ShiftAmount--) in LowerShifts()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 820 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
822 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
823 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
|
| D | LegalizeDAG.cpp | 388 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedStore() local
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
552 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedLoad() local
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 205 unsigned &ShiftAmount);
4214 const MCExpr *ShiftAmount; in parsePKHImm() local
4217 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
4221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
4297 const MCExpr *ShiftAmount; in parseShifterImm() local
4299 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
4303 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
4359 const MCExpr *ShiftAmount; in parseRotImm() local
4361 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
4365 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7111 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
7123 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
7714 int64_t ShiftAmount; in tryCombineShiftImm() local
7724 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
7726 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
7757 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) in tryCombineShiftImm()
7759 DAG.getConstant(-ShiftAmount, MVT::i32)); in tryCombineShiftImm()
7760 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) in tryCombineShiftImm()
7762 DAG.getConstant(ShiftAmount, MVT::i32)); in tryCombineShiftImm()
|
| D | AArch64ISelDAGToDAG.cpp | 1838 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
1868 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
1869 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
1874 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
|
| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 1564 SDValue ShiftAmount = in LowerLOAD() local
1572 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount); in LowerLOAD()
1573 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount); in LowerLOAD()
|