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Searched refs:Spill (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Davx-intel-ocl.ll69 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
70 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
71 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
72 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
73 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
74 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
75 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
76 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
77 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
78 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
[all …]
Dsse-intel-ocl.ll73 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
74 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
75 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
76 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
77 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
78 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
79 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
80 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
Davx512-intel-ocl.ll64 ; WIN64: vmovups %zmm21, {{.*(%rbp).*}} # 64-byte Spill
65 ; WIN64: vmovups %zmm6, {{.*(%rbp).*}} # 64-byte Spill
71 ; X64: kmovw %k7, {{.*}}(%rsp) ## 8-byte Folded Spill
72 ; X64: kmovw %k6, {{.*}}(%rsp) ## 8-byte Folded Spill
73 ; X64: kmovw %k5, {{.*}}(%rsp) ## 8-byte Folded Spill
74 ; X64: kmovw %k4, {{.*}}(%rsp) ## 8-byte Folded Spill
75 ; X64: vmovups %zmm31, {{.*}}(%rsp) ## 64-byte Spill
76 ; X64: vmovups %zmm16, {{.*}}(%rsp) ## 64-byte Spill
D2013-10-14-FastISel-incorrect-vreg.ll19 ; Spill %arg2.
21 ; Spill %loaded_ptr.
58 ; Spill %arg2.
60 ; Spill %loaded_ptr.
97 ; Spill %arg2.
99 ; Spill %loaded_ptr.
Dpmul.ll92 ; SSE2-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
93 ; SSE2-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
110 ; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
111 ; SSE41-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
128 ; ALL-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
129 ; ALL-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
Dunaligned-spill-folding.ll37 ; UNALIGNED: movdqu {{.*}} # 16-byte Folded Spill
42 ; ALIGNED: movdqa {{.*}} # 16-byte Spill
47 ; FORCEALIGNED: movdqa {{.*}} # 16-byte Spill
Dstatepoint-stackmap-format.ll73 ; Direct Spill Slot [RSP+0]
93 ; Direct Spill Slot [RSP+0]
98 ; Direct Spill Slot [RSP+0]
Dsink-cheap-instructions.ll7 ; CHECK: Spill
8 ; SINK-NOT: Spill
Dstatepoint-allocas.ll86 ; Direct Spill Slot [RSP+0]
110 ; Direct Spill Slot [RSP+0]
Dfold-tied-op.ll9 ; CHECK: shldl {{.*#+}} 4-byte Folded Spill
11 ; CHECK: shldl {{.*#+}} 4-byte Folded Spill
Dwin64_eh.ll162 ; WIN64: movaps %xmm7, -16(%rbp) # 16-byte Spill
164 ; WIN64: movaps %xmm6, -32(%rbp) # 16-byte Spill
Dlicm-regpressure.ll7 ; CHECK-NOT: Spill
/external/llvm/lib/Target/R600/
DSIMachineFunctionInfo.cpp51 struct SpilledReg Spill; in getSpilledReg() local
66 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; in getSpilledReg()
67 Spill.Lane = Lane; in getSpilledReg()
68 return Spill; in getSpilledReg()
DSIRegisterInfo.cpp218 struct SIMachineFunctionInfo::SpilledReg Spill = in eliminateFrameIndex() local
221 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
228 Spill.VGPR) in eliminateFrameIndex()
230 .addImm(Spill.Lane); in eliminateFrameIndex()
249 struct SIMachineFunctionInfo::SpilledReg Spill = in eliminateFrameIndex() local
252 if (Spill.VGPR == AMDGPU::NoRegister) { in eliminateFrameIndex()
263 .addReg(Spill.VGPR) in eliminateFrameIndex()
264 .addImm(Spill.Lane) in eliminateFrameIndex()
DSIMachineFunctionInfo.h58 void setHasSpilledVGPRs(bool Spill = true) { HasSpilledVGPRs = Spill; }
/external/llvm/lib/CodeGen/
DRegAllocBasic.cpp191 LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
194 if (!VRM->hasPhys(Spill.reg)) in spillInterferences()
199 Matrix->unassign(Spill); in spillInterferences()
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM); in spillInterferences()
/external/llvm/test/MC/Mips/
Delf-tls.s34 sw $ra, 20($sp) # 4-byte Folded Spill
66 sw $ra, 20($sp) # 4-byte Folded Spill
98 sw $ra, 20($sp) # 4-byte Folded Spill
Delf-N64.s34 sd $ra, 8($sp) # 8-byte Folded Spill
35 sd $gp, 0($sp) # 8-byte Folded Spill
Dr-mips-got-disp.s27 sd $ra, 8($sp) # 8-byte Folded Spill
28 sd $gp, 0($sp) # 8-byte Folded Spill
Dxgot.s38 sw $ra, 20($sp) # 4-byte Folded Spill
/external/llvm/test/CodeGen/Mips/
Dstldst.ll36 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
38 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll47 ; Spill 7 d-registers.
71 ; Spill 7 d-registers, leave a hole.
/external/llvm/test/CodeGen/AArch64/
Darm64-platform-reg.ll22 ; CHECK-RESERVE-X18: Spill
/external/llvm/test/CodeGen/Hexagon/
Dvalidate-offset.ll5 ; by 'Hexagon Expand Predicate Spill Code' pass.
/external/llvm/test/CodeGen/PowerPC/
Dsjlj.ll74 ; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
139 ; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill

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