/external/mesa3d/src/gallium/drivers/radeon/ |
D | R600ExpandSpecialInstrs.cpp | 97 unsigned Src0 = MI.getOperand(1).getReg(); in runOnMachineFunction() local 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction() 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction() 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction() 152 .addReg(Src0) in runOnMachineFunction()
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D | R600Instructions.td | 804 // Src0 = Input
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/external/llvm/lib/Target/AArch64/ |
D | AArch64AdvSIMDScalarPass.cpp | 203 unsigned Src0 = 0, SubReg0; in isProfitableToTransform() local 209 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform() 211 if (Src0) in isProfitableToTransform() 215 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) in isProfitableToTransform() 296 unsigned Src0 = 0, SubReg0; in transformInstruction() local 302 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction() 305 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) { in transformInstruction() 306 assert(Src0 && "Can't delete copy w/o a valid original source!"); in transformInstruction() 326 if (!Src0) { in transformInstruction() 328 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() [all …]
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D | AArch64FastISel.cpp | 4495 const Value *Src0 = I->getOperand(0); in selectMul() local 4497 if (const auto *C = dyn_cast<ConstantInt>(Src0)) in selectMul() 4499 std::swap(Src0, Src1); in selectMul() 4507 if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) { in selectMul() 4513 Src0 = ZExt->getOperand(0); in selectMul() 4516 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) { in selectMul() 4522 Src0 = SExt->getOperand(0); in selectMul() 4527 unsigned Src0Reg = getRegForValue(Src0); in selectMul() 4530 bool Src0IsKill = hasTrivialKill(Src0); in selectMul()
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/external/llvm/lib/Target/R600/ |
D | R600ExpandSpecialInstrs.cpp | 222 unsigned Src0 = BMI->getOperand( in runOnMachineFunction() local 228 (void) Src0; in runOnMachineFunction() 230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction() 232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction() 274 unsigned Src0 = MI.getOperand( in runOnMachineFunction() local 287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction() 293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction() 294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction() 328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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D | SIShrinkInstructions.cpp | 137 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local 141 if (Src0.isImm() && in foldImmediates() 142 TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx))) in foldImmediates() 148 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates() 152 if (Src0.isReg()) { in foldImmediates() 153 unsigned Reg = Src0.getReg(); in foldImmediates() 160 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
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D | SIInstrInfo.cpp | 735 unsigned Src0 = MI->getOperand(1).getReg(); in expandPostRAPseudo() local 740 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo() 744 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) in expandPostRAPseudo() 764 MachineOperand &Src0 = MI->getOperand(Src0Idx); in commuteInstruction() local 765 if (!Src0.isReg()) in commuteInstruction() 778 !isOperandLegal(MI, Src1Idx, &Src0))) { in commuteInstruction() 808 unsigned Reg = Src0.getReg(); in commuteInstruction() 809 unsigned SubReg = Src0.getSubReg(); in commuteInstruction() 811 Src0.ChangeToImmediate(Src1.getImm()); in commuteInstruction() 918 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0); in FoldImmediate() local [all …]
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D | R600InstrInfo.cpp | 1270 MachineOperand &Src0 = MI->getOperand( in buildSlotOfVectorInstruction() local 1275 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg()); in buildSlotOfVectorInstruction()
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D | AMDGPUISelLowering.cpp | 912 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator; in LowerINTRINSIC_WO_CHAIN() local 914 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0, in LowerINTRINSIC_WO_CHAIN() 2308 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, in constantFoldBFE() argument 2311 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width); in constantFoldBFE() 2316 return DAG.getConstant(Src0 >> Offset, MVT::i32); in constantFoldBFE()
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D | EvergreenInstructions.td | 267 // Src0 = Input
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 1011 SDValue Src0 = MLD->getSrc0(); in SplitVecRes_MLOAD() local 1013 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl); in SplitVecRes_MLOAD() 1358 SDValue Src0 = N->getOperand(1); in SplitVecOp_VSELECT() local 1360 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() 1374 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL); in SplitVecOp_VSELECT() 2440 SDValue Src0 = GetWidenedVector(N->getSrc0()); in WidenVecRes_MLOAD() local 2465 Mask, Src0, N->getMemoryVT(), in WidenVecRes_MLOAD()
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D | SelectionDAGBuilder.cpp | 3646 SDValue Src0 = getValue(I.getArgOperand(0)); in visitMaskedStore() local 3648 EVT VT = Src0.getValueType(); in visitMaskedStore() 3661 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT, in visitMaskedStore() 3673 SDValue Src0 = getValue(I.getArgOperand(3)); in visitMaskedLoad() local 3701 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO, in visitMaskedLoad()
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D | SelectionDAG.cpp | 5035 SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, in getMaskedLoad() argument 5039 SDValue Ops[] = { Chain, Ptr, Mask, Src0 }; in getMaskedLoad()
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D | DAGCombiner.cpp | 5095 SDValue Src0 = MLD->getSrc0(); in visitMLOAD() local 5097 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL); in visitMLOAD()
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/external/clang/lib/CodeGen/ |
D | CGBuiltin.cpp | 6383 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitUnaryFPBuiltin() local 6385 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType()); in emitUnaryFPBuiltin() 6386 return CGF.Builder.CreateCall(F, Src0); in emitUnaryFPBuiltin() 6393 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitTernaryFPBuiltin() local 6397 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType()); in emitTernaryFPBuiltin() 6398 return CGF.Builder.CreateCall3(F, Src0, Src1, Src2); in emitTernaryFPBuiltin() 6405 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); in emitFPIntBuiltin() local 6408 Value *F = CGF.CGM.getIntrinsic(IntrinsicID, Src0->getType()); in emitFPIntBuiltin() 6409 return CGF.Builder.CreateCall2(F, Src0, Src1); in emitFPIntBuiltin() 6445 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); in EmitR600BuiltinExpr() local [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | SelectionDAG.h | 854 SDValue Mask, SDValue Src0, EVT MemVT,
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/external/llvm/lib/CodeGen/ |
D | CodeGenPrepare.cpp | 1085 Value *Src0 = CI->getArgOperand(3); in ScalarizeMaskedLoad() local 1162 Value *NewI = Builder.CreateSelect(Mask, Phi, Src0); in ScalarizeMaskedLoad()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 14726 SDValue Src0 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local 14731 Mask, Src0, Subtarget, DAG); in LowerINTRINSIC_WO_CHAIN() 14736 SDValue Src0 = Op.getOperand(3); in LowerINTRINSIC_WO_CHAIN() local 14745 Mask, Src0, Subtarget, DAG); in LowerINTRINSIC_WO_CHAIN() 14752 Mask, Src0, Subtarget, DAG); in LowerINTRINSIC_WO_CHAIN()
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