Searched refs:Src1IsKill (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2565 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect() local
2573 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2574 Src1IsKill = true; in optimizeSelect()
2577 Src1IsKill, Src2Reg, Src2IsKill); in optimizeSelect()
2690 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect() local
2699 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2703 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4471 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem() local
4481 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4549 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul() local
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| D | AArch64InstrInfo.cpp | 2602 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMadd() local
2618 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMadd()
2652 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMaddR() local
2666 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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