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Searched refs:Tmp1 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp571 SDValue Tmp1 = Vec; in PerformInsertVectorEltInMemory() local
581 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory()
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, in PerformInsertVectorEltInMemory()
1560 SDValue Tmp1 = Node->getOperand(0); in ExpandFCOPYSIGN() local
1611 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); in ExpandFCOPYSIGN()
1626 SDValue Tmp1 = SDValue(Node, 0); in ExpandDYNAMIC_STACKALLOC() local
1629 SDValue Chain = Tmp1.getOperand(0); in ExpandDYNAMIC_STACKALLOC()
1642 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in ExpandDYNAMIC_STACKALLOC()
1644 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, in ExpandDYNAMIC_STACKALLOC()
1646 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in ExpandDYNAMIC_STACKALLOC()
[all …]
DLegalizeFloatTypes.cpp1416 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1417 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), in FloatExpandSetCCOperands()
1421 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1422 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), in FloatExpandSetCCOperands()
1426 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1427 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
DLegalizeVectorOps.cpp343 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); in LegalizeOp() local
344 if (Tmp1.getNode()) { in LegalizeOp()
345 Result = Tmp1; in LegalizeOp()
DLegalizeIntegerTypes.cpp2617 SDValue Tmp1, Tmp2; in IntegerExpandSetCCOperands() local
2620 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), in IntegerExpandSetCCOperands()
2622 if (!Tmp1.getNode()) in IntegerExpandSetCCOperands()
2623 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), in IntegerExpandSetCCOperands()
2634 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); in IntegerExpandSetCCOperands()
2657 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(), in IntegerExpandSetCCOperands()
2658 NewLHS, Tmp1, Tmp2); in IntegerExpandSetCCOperands()
/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/
Dcmsintrp.c842 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; in Eval4Inputs() local
932 … Tmp1[OutChan] = (cmsUInt16Number) c0 + ROUND_FIXED_TO_INT(_cmsToFixedDomain(Rest)); in Eval4Inputs()
1002 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]); in Eval4Inputs()
1023 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; in Eval4InputsFloat() local
1039 TetrahedralInterpFloat(Input + 1, Tmp1, &p1); in Eval4InputsFloat()
1047 cmsFloat32Number y0 = Tmp1[i]; in Eval4InputsFloat()
1067 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; in Eval5Inputs() local
1084 Eval4Inputs(Input + 1, Tmp1, &p1); in Eval5Inputs()
1093 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]); in Eval5Inputs()
1110 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; in Eval5InputsFloat() local
[all …]
/external/llvm/lib/CodeGen/
DIntrinsicLowering.cpp176 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
180 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
190 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
199 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
220 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
250 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
/external/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp132 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
135 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode()
136 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
137 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp); in generateSignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True); in generateUnsignedDivisionCode() local
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM() local
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
/external/llvm/lib/Target/R600/
DAMDGPUPromoteAlloca.cpp328 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ); in visitAlloca() local
329 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in visitAlloca()
DAMDGPUISelLowering.cpp1791 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM() local
1805 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
1821 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
1988 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC() local
1989 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2004 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT() local
2005 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2078 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, in LowerFROUND64() local
2082 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, in LowerFROUND64()
/external/clang/lib/StaticAnalyzer/Core/
DCheckerManager.cpp108 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
116 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2342 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2343 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2346 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2357 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2486 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2487 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2494 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2495 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2496 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2548 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/
Dstructs.h251 double Tmp1[MAXFFTSIZE]; member
Dfft.c338 …if (fftstate->Tmp0 == NULL || fftstate->Tmp1 == NULL || fftstate->Tmp2 == NULL || fftstate->Tmp3 =… in FFTRADIX()
345 Itmp = (REAL *) fftstate->Tmp1; in FFTRADIX()
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp1427 SmallVector<MachineOperand,2> Tmp1; in createPreheaderForLoop() local
1430 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false)) in createPreheaderForLoop()
1436 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false); in createPreheaderForLoop()
DHexagonISelLowering.cpp1098 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); in LowerLOAD() local
1099 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]); in LowerLOAD()
1119 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount); in LowerLOAD()
1120 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]); in LowerLOAD()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp3871 SDValue Tmp1 = Op.getOperand(1); in LowerFCOPYSIGN() local
3874 EVT SrcVT = Tmp1.getValueType(); in LowerFCOPYSIGN()
3892 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
3894 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3895 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3898 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, in LowerFCOPYSIGN()
3899 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
3902 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3911 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
3926 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
/external/llvm/lib/Support/
DAPInt.cpp797 unsigned Tmp1 = unsigned(VAL >> 16); in byteSwap() local
798 Tmp1 = ByteSwap_32(Tmp1); in byteSwap()
801 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1); in byteSwap()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1695 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
1699 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
1755 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
1759 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
1964 SDValue Tmp1 = ST->getChain(); in LowerSTOREi1() local
1972 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, in LowerSTOREi1()
/external/clang/lib/CodeGen/
DCGExprComplex.cpp773 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c in EmitBinDiv() local
775 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/external/llvm/test/CodeGen/R600/
Dudivrem.ll44 ; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]]
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp500 SDValue Tmp1, Tmp2; in SelectBitfieldInsert() local
2952 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
2955 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), in Select()
2966 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
2969 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), in Select()
DPPCISelLowering.cpp6389 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS() local
6392 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS()
6418 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS() local
6421 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS()
6446 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRA_PARTS() local
6449 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2753 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO() local
2754 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
/external/llvm/docs/
DCodingStandards.rst1156 Tire Tmp1 = M.makeTire(); // Bad -- 'Tmp1' provides no information.

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