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Searched refs:UnitSize (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h362 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
367 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
DPPCISelLowering.cpp1147 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMerge() argument
1151 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && in isVMerge()
1154 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units in isVMerge()
1155 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit in isVMerge()
1156 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), in isVMerge()
1157 LHSStart+j+i*UnitSize) || in isVMerge()
1158 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), in isVMerge()
1159 RHSStart+j+i*UnitSize)) in isVMerge()
1171 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMRGLShuffleMask() argument
1175 return isVMerge(N, UnitSize, 0, 0); in isVMRGLShuffleMask()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp7013 unsigned UnitSize = 0; in EmitStructByval() local
7021 UnitSize = 1; in EmitStructByval()
7023 UnitSize = 2; in EmitStructByval()
7029 UnitSize = 16; in EmitStructByval()
7031 UnitSize = 8; in EmitStructByval()
7034 if (UnitSize == 0) in EmitStructByval()
7035 UnitSize = 4; in EmitStructByval()
7039 bool IsNeon = UnitSize >= 8; in EmitStructByval()
7042 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass in EmitStructByval()
7043 : UnitSize == 8 ? &ARM::DPRRegClass in EmitStructByval()
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