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Searched refs:VIXL_ASSERT (Results 1 – 25 of 31) sorted by relevance

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/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h197 VIXL_ASSERT(IsValidComparison(*this, other));
201 VIXL_ASSERT(IsValidComparison(*this, other));
205 VIXL_ASSERT(IsValidComparison(*this, other));
209 VIXL_ASSERT(IsValidComparison(*this, other));
300 VIXL_ASSERT(IsValidBranchType(type)); in insert()
403 VIXL_ASSERT(!Done()); in Advance()
421 VIXL_ASSERT(!Done()); in AdvanceToNextType()
927 VIXL_ASSERT(allow_macro_instructions_); in Adr()
928 VIXL_ASSERT(!rd.IsZero()); in Adr()
933 VIXL_ASSERT(allow_macro_instructions_); in Adrp()
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Dassembler-a64.cc39 VIXL_ASSERT((1 << index) & list_); in PopLowestIndex()
46 VIXL_ASSERT(IsValid()); in PopHighestIndex()
52 VIXL_ASSERT((1 << index) & list_); in PopHighestIndex()
84 VIXL_ASSERT(type() == CPURegister::kNoRegister); in RemoveCalleeSaved()
85 VIXL_ASSERT(IsEmpty()); in RemoveCalleeSaved()
211 VIXL_ASSERT(code < kNumberOfRegisters); in WRegFromCode()
221 VIXL_ASSERT(code < kNumberOfRegisters); in XRegFromCode()
228 VIXL_ASSERT(code < kNumberOfVRegisters); in BRegFromCode()
234 VIXL_ASSERT(code < kNumberOfVRegisters); in HRegFromCode()
240 VIXL_ASSERT(code < kNumberOfVRegisters); in SRegFromCode()
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Dmacro-assembler-a64.cc35 VIXL_ASSERT(masm_->CursorOffset() < checkpoint_); in Release()
53 VIXL_ASSERT(IsEmpty()); in ~LiteralPool()
54 VIXL_ASSERT(!IsBlocked()); in ~LiteralPool()
83 VIXL_ASSERT(!IsBlocked()); in Emit()
84 VIXL_ASSERT(!IsEmpty()); in Emit()
91 VIXL_ASSERT(emit_size % kInstructionSize == 0); in Emit()
96 VIXL_ASSERT((pool_size % kWRegSizeInBytes) == 0); in Emit()
102 VIXL_ASSERT((*it)->IsUsed()); in Emit()
120 VIXL_ASSERT(masm_->CursorOffset() > first_use_); in AddEntry()
138 VIXL_ASSERT(IsEmpty() || in Release()
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Dassembler-a64.h63 VIXL_ASSERT(!IsValid()); in CPURegister()
64 VIXL_ASSERT(IsNone()); in CPURegister()
69 VIXL_ASSERT(IsValidOrNone()); in CPURegister()
73 VIXL_ASSERT(IsValid()); in code()
78 VIXL_ASSERT(IsValidOrNone()); in type()
83 VIXL_ASSERT(code_ < (sizeof(RegList) * 8)); in Bit()
88 VIXL_ASSERT(IsValid()); in size()
93 VIXL_ASSERT(IsValid()); in SizeInBytes()
94 VIXL_ASSERT(size() % 8 == 0); in SizeInBytes()
99 VIXL_ASSERT(IsValid()); in SizeInBits()
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Dinstructions-a64.cc53 VIXL_ASSERT(width <= 64); in RotateRight()
63 VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) || in RepeatBitsAcrossReg()
65 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in RepeatBitsAcrossReg()
238 VIXL_ASSERT((LSSize_offset + LSSize_width) == (kInstructionSize * 8)); in CalcLSDataSize()
305 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in ImmPCOffsetTarget()
309 VIXL_ASSERT(BranchType() != UnknownBranchType); in ImmPCOffsetTarget()
343 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADRP); in SetPCRelImmTarget()
355 VIXL_ASSERT(((target - this) & 3) == 0); in SetBranchImmTarget()
387 VIXL_ASSERT(IsWordAligned(source)); in SetImmLLiteral()
397 VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
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Ddecoder-a64.cc132 VIXL_ASSERT(*it == registered_visitor); in InsertVisitorBefore()
149 VIXL_ASSERT(*it == registered_visitor); in InsertVisitorAfter()
160 VIXL_ASSERT(instr->Bits(27, 24) == 0x0); in DecodePCRelAddressing()
163 VIXL_ASSERT(instr->Bit(28) == 0x1); in DecodePCRelAddressing()
169 VIXL_ASSERT((instr->Bits(27, 24) == 0x4) || in DecodeBranchSystemException()
270 VIXL_ASSERT((instr->Bits(27, 24) == 0x8) || in DecodeLoadStore()
393 VIXL_ASSERT(instr->Bits(27, 24) == 0x2); in DecodeLogical()
412 VIXL_ASSERT(instr->Bits(27, 24) == 0x3); in DecodeBitfieldExtract()
437 VIXL_ASSERT(instr->Bits(27, 24) == 0x1); in DecodeAddSubImmediate()
447 VIXL_ASSERT((instr->Bits(27, 24) == 0xA) || in DecodeDataProcessing()
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Ddebugger-a64.cc91 VIXL_ASSERT(tok->IsRegister()); in Cast()
113 VIXL_ASSERT(tok->IsFPRegister()); in Cast()
137 VIXL_ASSERT(tok->IsIdentifier()); in Cast()
155 VIXL_ASSERT(tok->IsAddress()); in Cast()
172 VIXL_ASSERT(tok->IsInteger()); in Cast()
199 VIXL_ASSERT(tok->IsFormat()); in Cast()
609 VIXL_ASSERT(count > 0); in PrintRegister()
631 VIXL_ASSERT(count > 0); in PrintFPRegister()
686 VIXL_ASSERT(end[1] == '\0'); in ReadCommandLine()
687 VIXL_ASSERT((end - buffer) < (length - 1)); in ReadCommandLine()
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Dcpu-a64.cc66 VIXL_ASSERT(is_uint32(cache_type_register)); in GetCacheType()
99 VIXL_ASSERT(IsPowerOf2(dsize)); in EnsureIAndDCacheCoherency()
100 VIXL_ASSERT(IsPowerOf2(isize)); in EnsureIAndDCacheCoherency()
Dinstructions-a64.h375 VIXL_ASSERT((uint64_t)(address) == address_raw); in LiteralAddress()
405 VIXL_ASSERT(IsWordAligned(this + offset)); in InstructionAtOffset()
535 VIXL_ASSERT(format0 != NULL);
541 VIXL_ASSERT(index <= (sizeof(formats_) / sizeof(formats_[0]))); in SetFormatMap()
542 VIXL_ASSERT(format != NULL); in SetFormatMap()
585 VIXL_ASSERT(GetNEONFormat(format_map) < (sizeof(vform) / sizeof(vform[0]))); in GetVectorFormat()
702 VIXL_ASSERT(mode == kPlaceholder); in GetSubstitute()
719 VIXL_ASSERT(format < (sizeof(formats) / sizeof(formats[0]))); in NEONFormatAsString()
725 VIXL_ASSERT((format == NF_B) || (format == NF_H) || in NEONFormatAsPlaceholder()
Dsimulator-a64.h171 VIXL_ASSERT((sign == 0) || (sign == 1)); in FPRound()
174 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPRound()
230 VIXL_ASSERT(sign_offset == (sizeof(T) * 8 - 1)); in FPRound()
253 VIXL_ASSERT(round_mode == FPRoundOdd); in FPRound()
286 VIXL_ASSERT(round_mode == FPRoundOdd); in FPRound()
287 VIXL_ASSERT(mantissa != 0); in FPRound()
326 VIXL_ASSERT(round_mode == FPRoundOdd); in FPRound()
364 VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || in Read()
374 VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || in Write()
405 VIXL_ASSERT(lane >= 0); in Insert()
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Ddisasm-a64.cc271 VIXL_ASSERT((reg_size == kXRegSize) || in IsMovzMovnImm()
1624 VIXL_ASSERT(index < (sizeof(mnemonics) / sizeof(mnemonics[0]))); in VisitNEON3Same()
1628 VIXL_ASSERT(mnemonic != NULL); in VisitNEON3Same()
2657 VIXL_ASSERT(reg.IsValid()); in AppendRegisterNameToOutput()
2663 VIXL_ASSERT(reg.IsVRegister()); in AppendRegisterNameToOutput()
2670 VIXL_ASSERT(reg.Is128Bits()); in AppendRegisterNameToOutput()
2751 VIXL_ASSERT(mnemonic != NULL); in Format()
2755 VIXL_ASSERT(buffer_pos_ < buffer_size_); in Format()
2759 VIXL_ASSERT(buffer_pos_ < buffer_size_); in Format()
2771 VIXL_ASSERT(buffer_pos_ < buffer_size_); in Substitute()
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Dsimulator-a64.cc39 VIXL_ASSERT(is_uintn(width, bits) || is_intn(width, bits)); in SetBits()
43 VIXL_ASSERT((mask & write_ignore_mask_) == 0); in SetBits()
64 VIXL_ASSERT((static_cast<int32_t>(-1) >> 1) == -1); in Simulator()
65 VIXL_ASSERT((static_cast<uint32_t>(-1) >> 1) == 0x7fffffff); in Simulator()
115 VIXL_ASSERT(IsSignallingNaN(rawbits_to_double(nan_bits & kDRegMask))); in ResetState()
116 VIXL_ASSERT(IsSignallingNaN(rawbits_to_float(nan_bits & kSRegMask))); in ResetState()
184 VIXL_ASSERT(code < kNumberOfRegisters); in WRegNameForCode()
194 VIXL_ASSERT(code < kNumberOfRegisters); in XRegNameForCode()
204 VIXL_ASSERT(code < kNumberOfFPRegisters); in SRegNameForCode()
210 VIXL_ASSERT(code < kNumberOfFPRegisters); in DRegNameForCode()
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Dlogic-a64.cc232 VIXL_ASSERT(round_mode == FPTieEven); in FPToFloat16()
282 VIXL_ASSERT(round_mode == FPTieEven); in FPToFloat16()
332 VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); in FPToFloat()
1389 VIXL_ASSERT(vform == kFormatD); in addp()
1605 VIXL_ASSERT(shift >= 0); in shl()
1616 VIXL_ASSERT(shift >= 0); in sshll()
1628 VIXL_ASSERT(shift >= 0); in sshll2()
1656 VIXL_ASSERT(shift >= 0); in ushll()
1668 VIXL_ASSERT(shift >= 0); in ushll2()
1697 VIXL_ASSERT(shift >= 0); in sqshl()
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Ddecoder-a64.h131 VIXL_ASSERT(!IsConstVisitor()); in MutableInstruction()
148 VIXL_ASSERT((*it)->IsConstVisitor()); in Decode()
Dcpu-a64.h49 VIXL_ASSERT(is_uintn(kAddressTagWidth, tag)); in SetPointerTag()
/external/vixl/test/
Dtest-utils-a64.h60 VIXL_ASSERT(sizeof(dump_.d_[0]) == kDRegSizeInBytes); in RegisterDump()
61 VIXL_ASSERT(sizeof(dump_.s_[0]) == kSRegSizeInBytes); in RegisterDump()
62 VIXL_ASSERT(sizeof(dump_.d_[0]) == kXRegSizeInBytes); in RegisterDump()
63 VIXL_ASSERT(sizeof(dump_.s_[0]) == kWRegSizeInBytes); in RegisterDump()
64 VIXL_ASSERT(sizeof(dump_.x_[0]) == kXRegSizeInBytes); in RegisterDump()
65 VIXL_ASSERT(sizeof(dump_.w_[0]) == kWRegSizeInBytes); in RegisterDump()
66 VIXL_ASSERT(sizeof(dump_.q_[0]) == kQRegSizeInBytes); in RegisterDump()
83 VIXL_ASSERT(RegAliasesMatch(code)); in wreg()
91 VIXL_ASSERT(RegAliasesMatch(code)); in xreg()
97 VIXL_ASSERT(FPRegAliasesMatch(code)); in sreg_bits()
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Dtest-utils-a64.cc121 VIXL_ASSERT(reg.Is32Bits()); in Equal32()
136 VIXL_ASSERT(reg.Is64Bits()); in Equal64()
146 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
156 VIXL_ASSERT(fpreg.Is32Bits()); in EqualFP32()
173 VIXL_ASSERT(fpreg.Is64Bits()); in EqualFP64()
181 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits()); in Equal64()
209 VIXL_ASSERT((expected & ~NZCVFlag) == 0); in EqualNzcv()
210 VIXL_ASSERT((result & ~NZCVFlag) == 0); in EqualNzcv()
266 VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count); in PopulateRegisterArray()
293 VIXL_ASSERT(CountSetBits(list, kNumberOfFPRegisters) == reg_count); in PopulateFPRegisterArray()
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Dtest-simulator-a64.cc193 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize)); in Test1Op_Helper()
194 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize)); in Test1Op_Helper()
244 VIXL_ASSERT(inputs_length > 0); in Test1Op()
285 VIXL_ASSERT(d == expected_length); in Test1Op()
298 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in Test2Op_Helper()
359 VIXL_ASSERT(inputs_length > 0); in Test2Op()
405 VIXL_ASSERT(d == expected_length); in Test2Op()
418 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in Test3Op_Helper()
489 VIXL_ASSERT(inputs_length > 0); in Test3Op()
540 VIXL_ASSERT(d == expected_length); in Test3Op()
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Dtest-runner.cc58 VIXL_ASSERT(last_ == NULL); in Test()
87 VIXL_ASSERT(IsOption(arg)); in NormalizeOption()
/external/vixl/src/vixl/
Dinvalset.h214 VIXL_ASSERT(monitor_ >= 0); in Release()
274 VIXL_ASSERT(monitor_ == 0); in ~InvalSet()
281 VIXL_ASSERT(monitor() == 0); in insert()
282 VIXL_ASSERT(IsValid(element)); in insert()
283 VIXL_ASSERT(Search(element) == NULL); in insert()
313 VIXL_ASSERT(monitor() == 0); in erase()
314 VIXL_ASSERT(IsValid(element)); in erase()
325 VIXL_ASSERT(monitor() == 0); in Search()
356 VIXL_ASSERT(monitor() == 0); in clear()
368 VIXL_ASSERT(monitor() == 0); in min_element()
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Dcode-buffer.cc39 VIXL_ASSERT(IsWordAligned(buffer_)); in CodeBuffer()
52 VIXL_ASSERT(buffer_ != NULL); in CodeBuffer()
57 VIXL_ASSERT(!IsDirty()); in ~CodeBuffer()
65 VIXL_ASSERT(RemainingBytes() > strlen(string)); in EmitString()
75 VIXL_ASSERT(end >= cursor_); in Align()
77 VIXL_ASSERT(RemainingBytes() >= padding_size); in Align()
78 VIXL_ASSERT(padding_size <= 4); in Align()
99 VIXL_ASSERT(managed_); in Grow()
100 VIXL_ASSERT(new_capacity > capacity_); in Grow()
Dutils.h47 VIXL_ASSERT((0 < n) && (n < 64)); in is_intn()
53 VIXL_ASSERT((0 < n) && (n < 64)); in is_uintn()
58 VIXL_ASSERT((0 < n) && (n < 64)); in truncate_to_intn()
158 VIXL_ASSERT(std::isnan(num)); in ToQuietNaN()
165 VIXL_ASSERT(std::isnan(num)); in ToQuietNaN()
188 VIXL_ASSERT(value != 0); in HighestSetBitPosition()
195 VIXL_ASSERT(IsPowerOf2(value)); in WhichPowerOf2()
205 VIXL_ASSERT(sizeof(pointer) == sizeof(intptr_t)); // NOLINT(runtime/sizeof) in IsWordAligned()
219 VIXL_ASSERT((pointer_raw + align_step) % alignment == 0); in AlignUp()
234 VIXL_ASSERT((pointer_raw - align_step) % alignment == 0); in AlignDown()
Dcode-buffer.h45 VIXL_ASSERT((offset >= 0) && (offset <= cursor_offset)); in OffsetFrom()
55 VIXL_ASSERT((offset >= 0) && (offset <= (cursor_ - buffer_))); in GetOffsetAddress()
60 VIXL_ASSERT((cursor_ >= buffer_) && (cursor_ <= (buffer_ + capacity_))); in RemainingBytes()
90 VIXL_ASSERT(RemainingBytes() >= sizeof(value)); in Emit()
Dcompiler-intrinsics.cc33 VIXL_ASSERT(IsPowerOf2(width) && (width <= 64)); in CountLeadingSignBitsFallBack()
43 VIXL_ASSERT(IsPowerOf2(width) && (width <= 64)); in CountLeadingZerosFallBack()
78 VIXL_ASSERT(IsPowerOf2(width) && (width <= 64)); in CountSetBitsFallBack()
113 VIXL_ASSERT(IsPowerOf2(width) && (width <= 64)); in CountTrailingZerosFallBack()
Dglobals.h77 #define VIXL_ASSERT(condition) assert(condition) macro
78 #define VIXL_CHECK(condition) VIXL_ASSERT(condition)
87 #define VIXL_ASSERT(condition) ((void) 0) macro

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