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Searched refs:WideVT (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp498 EVT WideVT = TLI.getPointerTy(); in ExpandLoad() local
500 assert(WideVT.isRound() && in ExpandLoad()
503 assert(WideVT.bitsGE(SrcEltVT) && in ExpandLoad()
506 unsigned WideBytes = WideVT.getStoreSize(); in ExpandLoad()
516 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR, in ExpandLoad()
523 EVT LoadVT = WideVT; in ExpandLoad()
528 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad()
547 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT); in ExpandLoad()
551 unsigned WideBits = WideVT.getSizeInBits(); in ExpandLoad()
557 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT)); in ExpandLoad()
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DLegalizeDAG.cpp3677 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); in ExpandNode() local
3693 } else if (TLI.isTypeLegal(WideVT)) { in ExpandNode()
3694 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); in ExpandNode()
3695 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); in ExpandNode()
3696 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); in ExpandNode()
3707 if (WideVT == MVT::i16) in ExpandNode()
3709 else if (WideVT == MVT::i32) in ExpandNode()
3711 else if (WideVT == MVT::i64) in ExpandNode()
3713 else if (WideVT == MVT::i128) in ExpandNode()
3730 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); in ExpandNode()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2488 EVT WideVT = MVT::i32; in lowerATOMIC_LOAD_OP() local
2489 if (NarrowVT == WideVT) in lowerATOMIC_LOAD_OP()
2515 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP()
2519 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in lowerATOMIC_LOAD_OP()
2520 DAG.getConstant(0, WideVT), BitShift); in lowerATOMIC_LOAD_OP()
2528 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
2529 DAG.getConstant(32 - BitSize, WideVT)); in lowerATOMIC_LOAD_OP()
2532 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
2533 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT)); in lowerATOMIC_LOAD_OP()
2536 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1206 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane() local
1210 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1258 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectPostLoadLane() local
1262 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2731 EVT WideVT = MVT::i128; in LowerUMULO_SMULO() local
2746 RTLIB::MUL_I128, WideVT, in LowerUMULO_SMULO()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp12669 EVT WideVT = WideVal.getValueType(); in EmitTest() local
12685 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
22105 EVT WideVT = N0->getOperand(0)->getValueType(0); in WidenMaskArithmetic() local
22106 if (WideVT != VT) in WidenMaskArithmetic()
22119 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) in WidenMaskArithmetic()
22125 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(), in WidenMaskArithmetic()
22127 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1); in WidenMaskArithmetic()
22128 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C); in WidenMaskArithmetic()
22134 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); in WidenMaskArithmetic()