Searched refs:X10 (Results 1 – 19 of 19) sorted by relevance
90 struct X10 { struct142 struct X10 x10; in use_structs()143 typedef int X10array[sizeof(struct X10)]; in use_structs()144 x10.y = sizeof(struct X10); in use_structs()
128 uint32_t X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15; in md4_block_data_order() local167 X10 = l; in md4_block_data_order()171 R0(C, D, A, B, X10, 11, 0); in md4_block_data_order()196 R1(C, D, A, B, X10, 9, 0x5A827999L); in md4_block_data_order()208 R2(D, A, B, C, X10, 9, 0x6ED9EBA1L); in md4_block_data_order()
210 struct X10 { struct211 virtual ~X10();214 struct X11 : X10 { // expected-error {{no suitable member 'operator delete' in 'X11'}}
230 #define X10 BITS2(1,0) macro7491 case X10: in math_WIDEN_LO_OR_HI_LANES()7540 case X10: amt = 32; break; in math_WIDEN_EVEN_OR_ODD_LANES()7676 case X10: in math_VEC_DUP_IMM()7889 vassert(size == X01 || size == X10); /* s or h only */ in math_SQDMULH()8421 if (size == X11 || (size == X10 && bitQ == 0)) return False; in dis_AdvSIMD_across_lanes()8465 if (size == X10 && bitQ == 0) return False; // 2s case not allowed in dis_AdvSIMD_across_lanes()8513 if ((size == X00 || size == X10) in dis_AdvSIMD_across_lanes()9311 vassert(size >= X00 && size <= X10); in dis_AdvSIMD_scalar_shift_by_imm()9365 vassert(size == X10 || size == X11); in dis_AdvSIMD_scalar_shift_by_imm()[all …]
2626 #define X10 BITS4(0,0, 1,0) macro3156 UInt instr = X_2_6_3_9_2_5_5(X10, X111000, isLoad ? X010 : X000, in do_load_or_store32()3171 UInt instr = X_2_6_2_12_5_5(X10, X111001, isLoad ? X01 : X00, in do_load_or_store32()3271 i->ARM64in.Arith.isAdd ? X10 : X11, in emit_ARM64Instr()3725 *p++ = X_2_6_2_12_5_5(X10, X010001, X00, simm12, X11111, X11111); in emit_ARM64Instr()3736 *p++ = X_2_6_2_12_5_5(X10, X010001, X00, 0, X11111, dd); in emit_ARM64Instr()3836 *p++ = X_2_6_2_12_5_5(X10, X111101, isLD ? X01 : X00, in emit_ARM64Instr()4113 = X_3_8_5_6_5_5(X000, X11110011, dM, (b1512 << 2) | X10, dN, dD); in emit_ARM64Instr()4136 = X_3_8_5_6_5_5(X000, X11110001, sM, (b1512 << 2) | X10, sN, sD); in emit_ARM64Instr()
41 case AArch64::X10: return AArch64::W10; in getWRegFromXReg()81 case AArch64::W10: return AArch64::X10; in getXRegFromWReg()
79 X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, enumConstant88 X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, enumConstant
132 #define X10(i) (((i)<<1)+((i)<<3)) macro
428 Int i=X10(hi)+lo; in uprv_decNumberToInt32()460 else return X10(hi)+lo; in uprv_decNumberToUInt32()630 exponent=X10(exponent)+(Int)*c-(Int)'0'; in uprv_decNumberFromString()692 out=X10(out)+(Int)*c-(Int)'0'; in uprv_decNumberFromString()3531 for (; cut>0; ub++, cut--) *up=X10(*up)+*ub; in uprv_decNumberSetBCD()5749 if (t<10) t=X10(t); /* adjust single-digit b */7036 discard1=quot-X10(temp);
159 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
933 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in942 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]965 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in974 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
96 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
2869 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerFormalArguments_64SVR4()3275 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerFormalArguments_Darwin()4564 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerCall_64SVR4()5258 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerCall_Darwin()
59 PPC::X8, PPC::X9, PPC::X10, PPC::X11,70 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
96 def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>;
363 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
14 #X10. Test C/C++ style {}-constructor
963 if (o == GOF(X10) && is48) return o; in get_otrack_shadow_offset_wrk()
1331 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" "X10 WW"