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Searched refs:andn (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dcr.ll78 declare i32 @llvm.hexagon.C2.andn(i32, i32)
80 %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
92 declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
94 %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
113 declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
115 %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
Dalu32_alu.ll48 declare i32 @llvm.hexagon.A4.andn(i32, i32)
50 %z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
Dxtype_alu.ll236 declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32)
238 %z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c)
243 declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32)
245 %z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c)
250 declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32)
252 %z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c)
/external/llvm/test/CodeGen/X86/
Dpeep-test-4.ll137 ; CHECK-LABEL: andn:
142 define void @andn(i32 %x, i32 %y) nounwind {
144 %andn = and i32 %y, %not
145 %cmp = icmp eq i32 %andn, 0
149 tail call void @foo(i32 %andn)
Dxor.ll180 ; X64: andn
182 ; X32: andn
/external/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s27 ! CHECK: andn %g1, %g2, %g3 ! encoding: [0x86,0x28,0x40,0x02]
28 andn %g1, %g2, %g3
/external/bison/lib/
Dbbitset.h136 void (*andn) (bitset, bitset, bitset); member
234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2)
/external/mesa3d/src/mesa/sparc/
Dxform.S75 andn %g3, 1, %o2
147 andn %g3, 1, %o2
190 andn %g3, 1, %o2
244 andn %g3, 1, %o2
292 andn %g3, 1, %o2
355 andn %g3, 1, %o2
406 andn %g3, 1, %o2
532 andn %g3, 1, %o2
601 andn %g3, 1, %o2
659 andn %g3, 1, %o2
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/external/llvm/test/MC/Disassembler/Sparc/
Dsparc.txt30 # CHECK: andn %g1, %g2, %g3
/external/llvm/test/CodeGen/SPARC/
D64bit.ll115 ; CHECK: andn [[R1]], %i0, %i0
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td467 "andn $rs1, $rs2, $rd",
471 "andn $rs1, $simm13, $rd", []>;
DSparcInstr64Bit.td151 "andn $b, $c, $dst",
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td1276 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1277 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
DX86InstrAVX512.td1891 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1901 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1940 defm : avx512_binop_pat<andn, KANDNWrr>;
DX86InstrSSE.td2896 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2933 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2994 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
/external/valgrind/
Dconfigure.ac2269 "andn %2, %1, %0" : "=r" (h) : "r" (0x1234567), "r" (0x7654321) );
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td133 let BaseOpcode = "andn_rr", CextOpcode = "andn" in