buffer_store_dword (reference) in projects: external

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Searched refs:buffer_store_dword (Results 1 – 25 of 77) sorted by relevance

12 3 4

/external/llvm/test/MC/R600/
D	mubuf.s	152 buffer_store_dword v1, s[4:7], s1 label 155 buffer_store_dword v1, s[4:7], s1 offset:4 label 158 buffer_store_dword v1, s[4:7], s1 offset:4 glc label 161 buffer_store_dword v1, s[4:7], s1 offset:4 slc label 164 buffer_store_dword v1, s[4:7], s1 offset:4 tfe label 167 buffer_store_dword v1, s[4:7], s1 tfe glc label 170 buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc label 173 buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4 label 180 buffer_store_dword v1, v2, s[4:7], s1 offen label 183 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 label [all …]
/external/llvm/test/CodeGen/R600/
D	reorder-stores.ll	`58 ; SI: buffer_store_dword 59 ; SI: buffer_store_dword 60 ; SI: buffer_store_dword 61 ; SI: buffer_store_dword 63 ; SI: buffer_store_dword 64 ; SI: buffer_store_dword 65 ; SI: buffer_store_dword 66 ; SI: buffer_store_dword 68 ; SI: buffer_store_dword 69 ; SI: buffer_store_dword [all …]`
D	copy-illegal-type.ll	`6 ; SI: buffer_store_dword [[REG]] 16 ; SI: buffer_store_dword [[REG]] 17 ; SI: buffer_store_dword [[REG]] 28 ; SI: buffer_store_dword [[REG]] 29 ; SI: buffer_store_dword [[REG]] 30 ; SI: buffer_store_dword [[REG]] 42 ; SI: buffer_store_dword [[REG]] 43 ; SI: buffer_store_dword [[REG]] 44 ; SI: buffer_store_dword [[REG]] 45 ; SI: buffer_store_dword [[REG]] [all …]`
D	work-item-intrinsics.ll	`12 ; GCN: buffer_store_dword [[VVAL]] 27 ; GCN: buffer_store_dword [[VVAL]] 42 ; GCN: buffer_store_dword [[VVAL]] 57 ; GCN: buffer_store_dword [[VVAL]] 72 ; GCN: buffer_store_dword [[VVAL]] 87 ; GCN: buffer_store_dword [[VVAL]] 102 ; GCN: buffer_store_dword [[VVAL]] 117 ; GCN: buffer_store_dword [[VVAL]] 132 ; GCN: buffer_store_dword [[VVAL]] 147 ; GCN: buffer_store_dword [[VVAL]] [all …]`
D	imm.ll	`39 ; CHECK-NEXT: buffer_store_dword [[REG]] 47 ; CHECK: buffer_store_dword [[REG]] 55 ; CHECK: buffer_store_dword [[REG]] 63 ; CHECK: buffer_store_dword [[REG]] 71 ; CHECK: buffer_store_dword [[REG]] 79 ; CHECK: buffer_store_dword [[REG]] 87 ; CHECK: buffer_store_dword [[REG]] 95 ; CHECK: buffer_store_dword [[REG]] 103 ; CHECK: buffer_store_dword [[REG]] 111 ; CHECK: buffer_store_dword [[REG]] [all …]`
D	global_atomics.ll	`14 ; SI: buffer_store_dword [[RET]] 35 ; SI: buffer_store_dword [[RET]] 55 ; SI: buffer_store_dword [[RET]] 74 ; SI: buffer_store_dword [[RET]] 94 ; SI: buffer_store_dword [[RET]] 115 ; SI: buffer_store_dword [[RET]] 135 ; SI: buffer_store_dword [[RET]] 154 ; SI: buffer_store_dword [[RET]] 174 ; SI: buffer_store_dword [[RET]] 195 ; SI: buffer_store_dword [[RET]] [all …]`
D	use-sgpr-multiple-times.ll	`12 ; GCN: buffer_store_dword [[RESULT]] 22 ; GCN: buffer_store_dword [[RESULT]] 36 ; GCN: buffer_store_dword [[RESULT]] 50 ; GCN: buffer_store_dword [[RESULT]] 64 ; GCN: buffer_store_dword [[RESULT]] 74 ; GCN: buffer_store_dword [[RESULT]] 84 ; GCN: buffer_store_dword [[RESULT]] 95 ; GCN: buffer_store_dword [[RESULT]]`
D	llvm.AMDGPU.bfe.i32.ll	`89 ; SI: buffer_store_dword [[VREG]], 184 ; SI: buffer_store_dword [[VREG]], 196 ; SI: buffer_store_dword [[VREG]], 208 ; SI: buffer_store_dword [[VREG]], 220 ; SI: buffer_store_dword [[VREG]], 232 ; SI: buffer_store_dword [[VREG]], 244 ; SI: buffer_store_dword [[VREG]], 256 ; SI: buffer_store_dword [[VREG]], 268 ; SI: buffer_store_dword [[VREG]], 280 ; SI: buffer_store_dword [[VREG]], [all …]`
D	si-triv-disjoint-mem-access.ll	`15 ; CI: buffer_store_dword 34 ; CI: buffer_store_dword 55 ; CI: buffer_store_dword 78 ; CI: buffer_store_dword 80 ; CI: buffer_store_dword 101 ; CI: buffer_store_dword 123 ; CI: buffer_store_dword 142 ; CI: buffer_store_dword 163 ; CI: buffer_store_dword 184 ; CI: buffer_store_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12 [all …]`
D	llvm.AMDGPU.bfe.u32.ll	`196 ; SI: buffer_store_dword [[VREG]], 332 ; SI: buffer_store_dword [[VREG]], 344 ; SI: buffer_store_dword [[VREG]], 356 ; SI: buffer_store_dword [[VREG]], 368 ; SI: buffer_store_dword [[VREG]], 380 ; SI: buffer_store_dword [[VREG]], 392 ; SI: buffer_store_dword [[VREG]], 404 ; SI: buffer_store_dword [[VREG]], 416 ; SI: buffer_store_dword [[VREG]], 428 ; SI: buffer_store_dword [[VREG]], [all …]`
D	shl_add_constant.ll	`10 ; SI: buffer_store_dword [[RESULT]] 25 ; SI-DAG: buffer_store_dword [[ADDREG]] 26 ; SI-DAG: buffer_store_dword [[SHLREG]] 44 ; SI: buffer_store_dword [[RESULT]] 63 ; SI: buffer_store_dword [[VRESULT]] 79 ; SI: buffer_store_dword [[VRESULT]]`
D	cvt_f32_ubyte.ll	`9 ; SI: buffer_store_dword [[CONV]], 140 ; SI: buffer_store_dword 141 ; SI: buffer_store_dword 142 ; SI: buffer_store_dword 143 ; SI: buffer_store_dword 144 ; SI: buffer_store_dword 145 ; SI: buffer_store_dword 146 ; SI: buffer_store_dword 147 ; SI: buffer_store_dword 159 ; SI: buffer_store_dword [[CONV]],`
D	llvm.AMDGPU.clamp.ll	`12 ; SI: buffer_store_dword [[RESULT]] 25 ; SI: buffer_store_dword [[RESULT]] 37 ; SI: buffer_store_dword [[RESULT]] 49 ; SI: buffer_store_dword [[RESULT]] 62 ; SI: buffer_store_dword [[RESULT]]`
D	commute_modifiers.ll	`10 ; SI-NEXT: buffer_store_dword [[REG]] 24 ; SI-NEXT: buffer_store_dword [[REG]] 39 ; SI-NEXT: buffer_store_dword [[REG]] 55 ; SI-NEXT: buffer_store_dword [[REG]] 70 ; SI-NEXT: buffer_store_dword [[REG]] 87 ; SI-NEXT: buffer_store_dword [[REG]] 104 ; SI-NEXT: buffer_store_dword [[REG]] 123 ; SI-NEXT: buffer_store_dword [[REG]] 141 ; SI-NEXT: buffer_store_dword [[REG]] 163 ; SI: buffer_store_dword [[RESULT]]`
D	ctpop.ll	`15 ; GCN: buffer_store_dword [[VRESULT]], 29 ; GCN: buffer_store_dword [[RESULT]], 46 ; GCN: buffer_store_dword [[RESULT]], 65 ; GCN-NEXT: buffer_store_dword [[RESULT]], 178 ; GCN: buffer_store_dword [[RESULT]], 193 ; GCN: buffer_store_dword [[RESULT]], 210 ; GCN: buffer_store_dword [[RESULT]], 224 ; GCN: buffer_store_dword [[RESULT]], 240 ; GCN: buffer_store_dword [[RESULT]], 257 ; GCN: buffer_store_dword [[RESULT]], [all …]`
D	llvm.AMDGPU.class.ll	`15 ; SI-NEXT: buffer_store_dword [[RESULT]] 30 ; SI-NEXT: buffer_store_dword [[RESULT]] 46 ; SI-NEXT: buffer_store_dword [[RESULT]] 62 ; SI-NEXT: buffer_store_dword [[RESULT]] 77 ; SI-NEXT: buffer_store_dword [[RESULT]] 90 ; SI-NEXT: buffer_store_dword [[RESULT]] 105 ; SI-NEXT: buffer_store_dword [[RESULT]] 119 ; SI-NEXT: buffer_store_dword [[RESULT]] 133 ; SI: buffer_store_dword [[RESULT]] 151 ; SI: buffer_store_dword [[RESULT]] [all …]`
D	fmuladd.ll	`38 ; CHECK: buffer_store_dword [[RESULT]] 57 ; CHECK: buffer_store_dword [[RESULT]] 76 ; CHECK: buffer_store_dword [[RESULT]] 98 ; CHECK: buffer_store_dword [[RESULT]] 120 ; CHECK: buffer_store_dword [[RESULT]] 140 ; CHECK: buffer_store_dword [[RESULT]] 162 ; CHECK: buffer_store_dword [[RESULT]] 184 ; CHECK: buffer_store_dword [[RESULT]]`
D	scratch-buffer.ll	`13 ; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen 15 ; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$… 51 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen 53 ; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$…`
D	llvm.AMDGPU.fract.ll	`16 ; GCN: buffer_store_dword [[RESULT]] 29 ; GCN: buffer_store_dword [[RESULT]] 42 ; GCN: buffer_store_dword [[RESULT]] 56 ; GCN: buffer_store_dword [[RESULT]]`
D	fmaxnum.ll	`126 ; SI: buffer_store_dword [[REG]] 140 ; SI: buffer_store_dword [[REG]] 155 ; SI: buffer_store_dword [[REG]] 169 ; SI: buffer_store_dword [[REG]] 183 ; SI: buffer_store_dword [[REG]] 197 ; SI: buffer_store_dword [[REG]] 211 ; SI: buffer_store_dword [[REG]] 225 ; SI: buffer_store_dword [[REG]]`
D	fminnum.ll	`125 ; SI: buffer_store_dword [[REG]] 139 ; SI: buffer_store_dword [[REG]] 154 ; SI: buffer_store_dword [[REG]] 168 ; SI: buffer_store_dword [[REG]] 182 ; SI: buffer_store_dword [[REG]] 196 ; SI: buffer_store_dword [[REG]] 210 ; SI: buffer_store_dword [[REG]] 224 ; SI: buffer_store_dword [[REG]]`
D	mubuf.ll	95 ; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x70,… 117 ; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x70… 128 ; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:4 ;… 138 ; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 145 ; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:40 154 ; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]] 171 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
D	missing-store.ll	`10 ; SI: buffer_store_dword 12 ; SI: buffer_store_dword`
D	mad-combine.ll	32 ; SI: buffer_store_dword [[RESULT]] 67 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 68 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … 105 ; SI: buffer_store_dword [[RESULT]] 135 ; SI: buffer_store_dword [[RESULT]] 170 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 171 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … 207 ; SI: buffer_store_dword [[RESULT]] 241 ; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 242 ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … [all …]
D	llvm.AMDGPU.div_scale.ll	`12 ; SI: buffer_store_dword [[RESULT0]] 32 ; SI: buffer_store_dword [[RESULT0]] 92 ; SI: buffer_store_dword [[RESULT0]] 110 ; SI: buffer_store_dword [[RESULT0]] 128 ; SI: buffer_store_dword [[RESULT0]] 146 ; SI: buffer_store_dword [[RESULT0]] 237 ; SI: buffer_store_dword [[RESULT0]] 251 ; SI: buffer_store_dword [[RESULT0]] 293 ; SI: buffer_store_dword [[RESULT0]] 309 ; SI: buffer_store_dword [[RESULT0]] [all …]`

12 3 4

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