1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=CHECK %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CHECK %s 3 4; Use a 64-bit value with lo bits that can be represented as an inline constant 5; CHECK-LABEL: {{^}}i64_imm_inline_lo: 6; CHECK: s_mov_b32 [[LO:s[0-9]+]], 5 7; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], [[LO]] 8; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]: 9define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { 10entry: 11 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 12 ret void 13} 14 15; Use a 64-bit value with hi bits that can be represented as an inline constant 16; CHECK-LABEL: {{^}}i64_imm_inline_hi: 17; CHECK: s_mov_b32 [[HI:s[0-9]+]], 5 18; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], [[HI]] 19; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]] 20define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { 21entry: 22 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 23 ret void 24} 25 26; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64: 27; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000 28; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}} 29; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] 30; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] 31; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 32define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) { 33 store i64 -9223372036854775808, i64 addrspace(1) *%out 34 ret void 35} 36 37; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32: 38; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 39; CHECK-NEXT: buffer_store_dword [[REG]] 40define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) { 41 store i32 -2147483648, i32 addrspace(1)* %out 42 ret void 43} 44 45; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32: 46; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} 47; CHECK: buffer_store_dword [[REG]] 48define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { 49 store float 0.0, float addrspace(1)* %out 50 ret void 51} 52 53; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32: 54; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 55; CHECK: buffer_store_dword [[REG]] 56define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) { 57 store float -0.0, float addrspace(1)* %out 58 ret void 59} 60 61; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32: 62; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}} 63; CHECK: buffer_store_dword [[REG]] 64define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) { 65 store float 0.5, float addrspace(1)* %out 66 ret void 67} 68 69; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32: 70; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}} 71; CHECK: buffer_store_dword [[REG]] 72define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) { 73 store float -0.5, float addrspace(1)* %out 74 ret void 75} 76 77; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32: 78; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} 79; CHECK: buffer_store_dword [[REG]] 80define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) { 81 store float 1.0, float addrspace(1)* %out 82 ret void 83} 84 85; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32: 86; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} 87; CHECK: buffer_store_dword [[REG]] 88define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) { 89 store float -1.0, float addrspace(1)* %out 90 ret void 91} 92 93; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32: 94; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}} 95; CHECK: buffer_store_dword [[REG]] 96define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) { 97 store float 2.0, float addrspace(1)* %out 98 ret void 99} 100 101; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32: 102; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}} 103; CHECK: buffer_store_dword [[REG]] 104define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) { 105 store float -2.0, float addrspace(1)* %out 106 ret void 107} 108 109; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32: 110; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}} 111; CHECK: buffer_store_dword [[REG]] 112define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) { 113 store float 4.0, float addrspace(1)* %out 114 ret void 115} 116 117; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32: 118; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}} 119; CHECK: buffer_store_dword [[REG]] 120define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) { 121 store float -4.0, float addrspace(1)* %out 122 ret void 123} 124 125; CHECK-LABEL: {{^}}store_literal_imm_f32: 126; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000 127; CHECK: buffer_store_dword [[REG]] 128define void @store_literal_imm_f32(float addrspace(1)* %out) { 129 store float 4096.0, float addrspace(1)* %out 130 ret void 131} 132 133; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32: 134; CHECK: s_load_dword [[VAL:s[0-9]+]] 135; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}} 136; CHECK: buffer_store_dword [[REG]] 137define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { 138 %y = fadd float %x, 0.0 139 store float %y, float addrspace(1)* %out 140 ret void 141} 142 143; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32: 144; CHECK: s_load_dword [[VAL:s[0-9]+]] 145; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}} 146; CHECK: buffer_store_dword [[REG]] 147define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { 148 %y = fadd float %x, 0.5 149 store float %y, float addrspace(1)* %out 150 ret void 151} 152 153; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32: 154; CHECK: s_load_dword [[VAL:s[0-9]+]] 155; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}} 156; CHECK: buffer_store_dword [[REG]] 157define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { 158 %y = fadd float %x, -0.5 159 store float %y, float addrspace(1)* %out 160 ret void 161} 162 163; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32: 164; CHECK: s_load_dword [[VAL:s[0-9]+]] 165; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}} 166; CHECK: buffer_store_dword [[REG]] 167define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { 168 %y = fadd float %x, 1.0 169 store float %y, float addrspace(1)* %out 170 ret void 171} 172 173; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32: 174; CHECK: s_load_dword [[VAL:s[0-9]+]] 175; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}} 176; CHECK: buffer_store_dword [[REG]] 177define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { 178 %y = fadd float %x, -1.0 179 store float %y, float addrspace(1)* %out 180 ret void 181} 182 183; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32: 184; CHECK: s_load_dword [[VAL:s[0-9]+]] 185; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}} 186; CHECK: buffer_store_dword [[REG]] 187define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { 188 %y = fadd float %x, 2.0 189 store float %y, float addrspace(1)* %out 190 ret void 191} 192 193; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32: 194; CHECK: s_load_dword [[VAL:s[0-9]+]] 195; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}} 196; CHECK: buffer_store_dword [[REG]] 197define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { 198 %y = fadd float %x, -2.0 199 store float %y, float addrspace(1)* %out 200 ret void 201} 202 203; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32: 204; CHECK: s_load_dword [[VAL:s[0-9]+]] 205; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}} 206; CHECK: buffer_store_dword [[REG]] 207define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { 208 %y = fadd float %x, 4.0 209 store float %y, float addrspace(1)* %out 210 ret void 211} 212 213; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32: 214; CHECK: s_load_dword [[VAL:s[0-9]+]] 215; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}} 216; CHECK: buffer_store_dword [[REG]] 217define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { 218 %y = fadd float %x, -4.0 219 store float %y, float addrspace(1)* %out 220 ret void 221} 222 223; CHECK-LABEL: {{^}}commute_add_inline_imm_0.5_f32: 224; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 225; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] 226; CHECK: buffer_store_dword [[REG]] 227define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 228 %x = load float, float addrspace(1)* %in 229 %y = fadd float %x, 0.5 230 store float %y, float addrspace(1)* %out 231 ret void 232} 233 234; CHECK-LABEL: {{^}}commute_add_literal_f32: 235; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 236; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] 237; CHECK: buffer_store_dword [[REG]] 238define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 239 %x = load float, float addrspace(1)* %in 240 %y = fadd float %x, 1024.0 241 store float %y, float addrspace(1)* %out 242 ret void 243} 244 245; CHECK-LABEL: {{^}}add_inline_imm_1_f32: 246; CHECK: s_load_dword [[VAL:s[0-9]+]] 247; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}} 248; CHECK: buffer_store_dword [[REG]] 249define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) { 250 %y = fadd float %x, 0x36a0000000000000 251 store float %y, float addrspace(1)* %out 252 ret void 253} 254 255; CHECK-LABEL: {{^}}add_inline_imm_2_f32: 256; CHECK: s_load_dword [[VAL:s[0-9]+]] 257; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}} 258; CHECK: buffer_store_dword [[REG]] 259define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) { 260 %y = fadd float %x, 0x36b0000000000000 261 store float %y, float addrspace(1)* %out 262 ret void 263} 264 265; CHECK-LABEL: {{^}}add_inline_imm_16_f32: 266; CHECK: s_load_dword [[VAL:s[0-9]+]] 267; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]] 268; CHECK: buffer_store_dword [[REG]] 269define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) { 270 %y = fadd float %x, 0x36e0000000000000 271 store float %y, float addrspace(1)* %out 272 ret void 273} 274 275; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32: 276; CHECK: s_load_dword [[VAL:s[0-9]+]] 277; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]] 278; CHECK: buffer_store_dword [[REG]] 279define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) { 280 %y = fadd float %x, 0xffffffffe0000000 281 store float %y, float addrspace(1)* %out 282 ret void 283} 284 285; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32: 286; CHECK: s_load_dword [[VAL:s[0-9]+]] 287; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]] 288; CHECK: buffer_store_dword [[REG]] 289define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) { 290 %y = fadd float %x, 0xffffffffc0000000 291 store float %y, float addrspace(1)* %out 292 ret void 293} 294 295; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32: 296; CHECK: s_load_dword [[VAL:s[0-9]+]] 297; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]] 298; CHECK: buffer_store_dword [[REG]] 299define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) { 300 %y = fadd float %x, 0xfffffffe00000000 301 store float %y, float addrspace(1)* %out 302 ret void 303} 304 305; CHECK-LABEL: {{^}}add_inline_imm_63_f32: 306; CHECK: s_load_dword [[VAL:s[0-9]+]] 307; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]] 308; CHECK: buffer_store_dword [[REG]] 309define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) { 310 %y = fadd float %x, 0x36ff800000000000 311 store float %y, float addrspace(1)* %out 312 ret void 313} 314 315; CHECK-LABEL: {{^}}add_inline_imm_64_f32: 316; CHECK: s_load_dword [[VAL:s[0-9]+]] 317; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]] 318; CHECK: buffer_store_dword [[REG]] 319define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) { 320 %y = fadd float %x, 0x3700000000000000 321 store float %y, float addrspace(1)* %out 322 ret void 323} 324 325 326; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64: 327; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 328; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 329; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]] 330; CHECK: buffer_store_dwordx2 [[REG]] 331define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { 332 %y = fadd double %x, 0.0 333 store double %y, double addrspace(1)* %out 334 ret void 335} 336 337; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64: 338; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 339; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 340; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]] 341; CHECK: buffer_store_dwordx2 [[REG]] 342define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { 343 %y = fadd double %x, 0.5 344 store double %y, double addrspace(1)* %out 345 ret void 346} 347 348; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64: 349; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 350; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 351; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]] 352; CHECK: buffer_store_dwordx2 [[REG]] 353define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { 354 %y = fadd double %x, -0.5 355 store double %y, double addrspace(1)* %out 356 ret void 357} 358 359; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64: 360; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 361; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 362; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]] 363; CHECK: buffer_store_dwordx2 [[REG]] 364define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { 365 %y = fadd double %x, 1.0 366 store double %y, double addrspace(1)* %out 367 ret void 368} 369 370; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64: 371; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 372; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 373; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]] 374; CHECK: buffer_store_dwordx2 [[REG]] 375define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { 376 %y = fadd double %x, -1.0 377 store double %y, double addrspace(1)* %out 378 ret void 379} 380 381; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64: 382; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 383; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 384; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]] 385; CHECK: buffer_store_dwordx2 [[REG]] 386define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { 387 %y = fadd double %x, 2.0 388 store double %y, double addrspace(1)* %out 389 ret void 390} 391 392; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64: 393; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 394; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 395; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]] 396; CHECK: buffer_store_dwordx2 [[REG]] 397define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { 398 %y = fadd double %x, -2.0 399 store double %y, double addrspace(1)* %out 400 ret void 401} 402 403; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64: 404; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 405; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 406; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]] 407; CHECK: buffer_store_dwordx2 [[REG]] 408define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { 409 %y = fadd double %x, 4.0 410 store double %y, double addrspace(1)* %out 411 ret void 412} 413 414; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64: 415; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 416; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 417; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]] 418; CHECK: buffer_store_dwordx2 [[REG]] 419define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { 420 %y = fadd double %x, -4.0 421 store double %y, double addrspace(1)* %out 422 ret void 423} 424 425 426; CHECK-LABEL: {{^}}add_inline_imm_1_f64: 427; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 428; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 429; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]] 430; CHECK: buffer_store_dwordx2 [[REG]] 431define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { 432 %y = fadd double %x, 0x0000000000000001 433 store double %y, double addrspace(1)* %out 434 ret void 435} 436 437; CHECK-LABEL: {{^}}add_inline_imm_2_f64: 438; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 439; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 440; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]] 441; CHECK: buffer_store_dwordx2 [[REG]] 442define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { 443 %y = fadd double %x, 0x0000000000000002 444 store double %y, double addrspace(1)* %out 445 ret void 446} 447 448; CHECK-LABEL: {{^}}add_inline_imm_16_f64: 449; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 450; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 451; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]] 452; CHECK: buffer_store_dwordx2 [[REG]] 453define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { 454 %y = fadd double %x, 0x0000000000000010 455 store double %y, double addrspace(1)* %out 456 ret void 457} 458 459; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64: 460; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 461; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 462; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]] 463; CHECK: buffer_store_dwordx2 [[REG]] 464define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { 465 %y = fadd double %x, 0xffffffffffffffff 466 store double %y, double addrspace(1)* %out 467 ret void 468} 469 470; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64: 471; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 472; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 473; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]] 474; CHECK: buffer_store_dwordx2 [[REG]] 475define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { 476 %y = fadd double %x, 0xfffffffffffffffe 477 store double %y, double addrspace(1)* %out 478 ret void 479} 480 481; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64: 482; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 483; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 484; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]] 485; CHECK: buffer_store_dwordx2 [[REG]] 486define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { 487 %y = fadd double %x, 0xfffffffffffffff0 488 store double %y, double addrspace(1)* %out 489 ret void 490} 491 492; CHECK-LABEL: {{^}}add_inline_imm_63_f64: 493; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 494; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 495; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]] 496; CHECK: buffer_store_dwordx2 [[REG]] 497define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { 498 %y = fadd double %x, 0x000000000000003F 499 store double %y, double addrspace(1)* %out 500 ret void 501} 502 503; CHECK-LABEL: {{^}}add_inline_imm_64_f64: 504; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 505; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 506; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]] 507; CHECK: buffer_store_dwordx2 [[REG]] 508define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { 509 %y = fadd double %x, 0x0000000000000040 510 store double %y, double addrspace(1)* %out 511 ret void 512} 513 514 515; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64: 516; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0 517; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0 518; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 519define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { 520 store double 0.0, double addrspace(1)* %out 521 ret void 522} 523 524 525; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64: 526; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x80000000 527; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}} 528; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] 529; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] 530; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 531define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) { 532 store double -0.0, double addrspace(1)* %out 533 ret void 534} 535 536; CHECK-LABEL: {{^}}store_inline_imm_0.5_f64: 537; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 538; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000 539; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 540define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) { 541 store double 0.5, double addrspace(1)* %out 542 ret void 543} 544 545; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f64: 546; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 547; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000 548; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 549define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) { 550 store double -0.5, double addrspace(1)* %out 551 ret void 552} 553 554; CHECK-LABEL: {{^}}store_inline_imm_1.0_f64: 555; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 556; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000 557; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 558define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) { 559 store double 1.0, double addrspace(1)* %out 560 ret void 561} 562 563; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f64: 564; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 565; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000 566; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 567define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) { 568 store double -1.0, double addrspace(1)* %out 569 ret void 570} 571 572; CHECK-LABEL: {{^}}store_inline_imm_2.0_f64: 573; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 574; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0 575; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 576define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) { 577 store double 2.0, double addrspace(1)* %out 578 ret void 579} 580 581; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f64: 582; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 583; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0 584; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 585define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) { 586 store double -2.0, double addrspace(1)* %out 587 ret void 588} 589 590; CHECK-LABEL: {{^}}store_inline_imm_4.0_f64: 591; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 592; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000 593; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 594define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) { 595 store double 4.0, double addrspace(1)* %out 596 ret void 597} 598 599; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f64: 600; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 601; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000 602; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 603define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) { 604 store double -4.0, double addrspace(1)* %out 605 ret void 606} 607 608; CHECK-LABEL: {{^}}store_literal_imm_f64: 609; CHECK-DAG: s_mov_b32 s[[HI_SREG:[0-9]+]], 0x40b00000 610; CHECK-DAG: s_mov_b32 s[[LO_SREG:[0-9]+]], 0{{$}} 611; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] 612; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] 613; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 614define void @store_literal_imm_f64(double addrspace(1)* %out) { 615 store double 4096.0, double addrspace(1)* %out 616 ret void 617} 618