Searched refs:cacheline (Results 1 – 8 of 8) sorted by relevance
258 util_cpu_caps.cacheline = 32; in util_cpu_detect()264 unsigned int cacheline; in util_cpu_detect() local284 cacheline = ((regs2[1] >> 8) & 0xFF) * 8; in util_cpu_detect()285 if (cacheline > 0) in util_cpu_detect()286 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()303 util_cpu_caps.cacheline = regs2[2] & 0xFF; in util_cpu_detect()324 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline); in util_cpu_detect()
53 unsigned cacheline; member
293 * In addition, this controls the spacing of cacheline-spaced size classes.302 /* Return the smallest cacheline multiple that is >= s. */
351 Make sure the instruction which starts a loop does not cross a cacheline355 In the new trace, the hot loop has an instruction which crosses a cacheline358 to grab the bytes from the next cacheline.
974 uint alignment = MAX2(16, util_cpu_caps.cacheline); in alloc_image_data()
106 …ne into state tracker objects: this would allow them to fit in the same cacheline and improve perf…
425 "arenas.cacheline", "arenas.subpage", "arenas.[tqcs]space_{min,max}", and
5063 + * the cache/cacheline performance unclear.