Searched refs:constrainOperandRegClass (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 294 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
317 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
318 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
346 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rrr()
347 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rrr()
348 Op2 = constrainOperandRegClass(II, Op1, 3); in fastEmitInst_rrr()
377 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
404 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
405 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
572 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1693 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1725 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1747 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1748 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1772 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1773 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1774 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1798 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1845 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rf()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1065 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1067 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1257 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1258 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1302 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1338 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1339 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1378 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1379 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2017 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 474 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
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