Home
last modified time | relevance | path

Searched refs:dmtc1 (Results 1 – 25 of 46) sorted by relevance

12

/external/valgrind/none/tests/mips64/
Dmove_instructions.stdout.exp-BE2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b502
[all …]
Dmove_instructions.stdout.exp-LE2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b502
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn-hard-fp128.ll24 ; N32-DAG: dmtc1 [[R2]], $f0
25 ; N32-DAG: dmtc1 [[R4]], $f2
30 ; N64-DAG: dmtc1 [[R3]], $f0
31 ; N64-DAG: dmtc1 [[R4]], $f2
Dreturn-hard-struct-f128.ll27 ; N32-DAG: dmtc1 [[R2]], $f0
30 ; N32-DAG: dmtc1 [[R4]], $f1
34 ; N64-DAG: dmtc1 [[R2]], $f0
36 ; N64-DAG: dmtc1 [[R4]], $f1
/external/llvm/test/CodeGen/Mips/
Dint-to-float-conversion.ll32 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
42 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
Dfcopysign-f32-f64.ll43 ; 64: dmtc1 $[[OR]], $f0
47 ; 64R2: dmtc1 $[[INS]], $f0
Dfcopysign.ll28 ; 64: dmtc1 $[[OR]], $f0
32 ; 64R2: dmtc1 $[[INS]], $f0
Dfpxx.ll43 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
140 ; 4-NOFPXX: dmtc1 $zero, $f0
142 ; 64-NOFPXX: dmtc1 $zero, $f0
178 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
181 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
Dmips64fpimm0.ll6 ; CHECK: dmtc1 $zero
Dfmadd1.ll219 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
260 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
308 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
356 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
Danalyzebranch.ll18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
/external/llvm/test/MC/Disassembler/Mips/
Dmips64_le.txt17 # CHECK: dmtc1 $23, $f5
Dmips64r2_le.txt17 # CHECK: dmtc1 $23, $f5
Dmips64r2.txt17 # CHECK: dmtc1 $23, $f5
Dmips64.txt20 # CHECK: dmtc1 $23, $f5
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll159 ; DMTC-DAG: dmtc1 $zero, $f0
190 ; DMTC-DAG: dmtc1 $zero, $f0
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s23 …dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips5.s23 …dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips4.s23 …dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s27 …dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s25 …dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips3/
Dvalid.s77 dmtc1 $s0,$f14
/external/llvm/test/MC/Mips/mips4/
Dvalid.s81 dmtc1 $s0,$f14
/external/llvm/test/MC/Mips/mips5/
Dvalid.s81 dmtc1 $s0,$f14
/external/llvm/test/MC/Mips/mips64/
Dvalid.s86 dmtc1 $s0,$f14

12