1; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
2; correctly.
3; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the
4; the Has2008 and ABS2008 configuration bits which govern the conformance to
5; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
6; available when -enable-no-nans-fp-math is given.
7
8; RUN: llc < %s -march=mipsel   -mcpu=mips32              -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32   -check-prefix=32-NONAN
9; RUN: llc < %s -march=mipsel   -mcpu=mips32r2            -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN
10; RUN: llc < %s -march=mipsel   -mcpu=mips32r6            -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN
11; RUN: llc < %s -march=mips64el -mcpu=mips64   -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NONAN
12; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
13; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
14; RUN: llc < %s -march=mipsel   -mcpu=mips32              | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN
15; RUN: llc < %s -march=mipsel   -mcpu=mips32r2            | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN
16; RUN: llc < %s -march=mipsel   -mcpu=mips32r6            | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN
17; RUN: llc < %s -march=mips64el -mcpu=mips64   -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64   -check-prefix=64-NAN
18; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
19; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
20
21define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
22entry:
23; ALL-LABEL: FOO0float:
24
25; 32-DAG:        mtc1 $6, $[[T0:f[0-9]+]]
26; 32-DAG:        mul.s $[[T1:f[0-9]+]], $f12, $f14
27; 32-DAG:        add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
28; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
29; 32-DAG:        add.s $f0, $[[T1]], $[[T2]]
30
31; 32R2:          mtc1 $6, $[[T0:f[0-9]+]]
32; 32R2:          madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
33; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
34; 32R2:          add.s $f0, $[[T1]], $[[T2]]
35
36; 32R6-DAG:      mtc1 $6, $[[T0:f[0-9]+]]
37; 32R6-DAG:      mul.s $[[T1:f[0-9]+]], $f12, $f14
38; 32R6-DAG:      add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
39; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
40; 32R6-DAG:      add.s $f0, $[[T1]], $[[T2]]
41
42; 64-DAG:        madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
43; 64-DAG:        mtc1 $zero, $[[T1:f[0-9]+]]
44; 64-DAG:        add.s $f0, $[[T0]], $[[T1]]
45
46; 64R2:          madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
47; 64R2:          mtc1 $zero, $[[T1:f[0-9]+]]
48; 64R2:          add.s $f0, $[[T0]], $[[T1]]
49
50; 64R6-DAG:      mul.s $[[T0:f[0-9]+]], $f12, $f13
51; 64R6-DAG:      add.s $[[T1:f[0-9]+]], $[[T0]], $f14
52; 64R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
53; 64R6-DAG:      add.s $f0, $[[T1]], $[[T2]]
54
55  %mul = fmul float %a, %b
56  %add = fadd float %mul, %c
57  %add1 = fadd float %add, 0.000000e+00
58  ret float %add1
59}
60
61define float @FOO1float(float %a, float %b, float %c) nounwind readnone {
62entry:
63; ALL-LABEL: FOO1float:
64
65; 32-DAG:        mtc1 $6, $[[T0:f[0-9]+]]
66; 32-DAG:        mul.s $[[T1:f[0-9]+]], $f12, $f14
67; 32-DAG:        sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
68; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
69; 32-DAG:        add.s $f0, $[[T1]], $[[T2]]
70
71; 32R2:          mtc1 $6, $[[T0:f[0-9]+]]
72; 32R2:          msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
73; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
74; 32R2:          add.s $f0, $[[T1]], $[[T2]]
75
76; 32R6-DAG:      mtc1 $6, $[[T0:f[0-9]+]]
77; 32R6-DAG:      mul.s $[[T1:f[0-9]+]], $f12, $f14
78; 32R6-DAG:      sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
79; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
80; 32R6-DAG:      add.s $f0, $[[T1]], $[[T2]]
81
82; 64-DAG:        msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
83; 64-DAG:        mtc1 $zero, $[[T1:f[0-9]+]]
84; 64-DAG:        add.s $f0, $[[T0]], $[[T1]]
85
86; 64R2:          msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
87; 64R2:          mtc1 $zero, $[[T1:f[0-9]+]]
88; 64R2:          add.s $f0, $[[T0]], $[[T1]]
89
90; 64R6-DAG:      mul.s $[[T0:f[0-9]+]], $f12, $f13
91; 64R6-DAG:      sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
92; 64R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
93; 64R6-DAG:      add.s $f0, $[[T1]], $[[T2]]
94
95  %mul = fmul float %a, %b
96  %sub = fsub float %mul, %c
97  %add = fadd float %sub, 0.000000e+00
98  ret float %add
99}
100
101define float @FOO2float(float %a, float %b, float %c) nounwind readnone {
102entry:
103; ALL-LABEL: FOO2float:
104
105; 32-DAG:        mtc1 $6, $[[T0:f[0-9]+]]
106; 32-DAG:        mul.s $[[T1:f[0-9]+]], $f12, $f14
107; 32-DAG:        add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
108; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
109; 32-DAG:        sub.s $f0, $[[T2]], $[[T1]]
110
111; 32R2-NONAN:    mtc1 $6, $[[T0:f[0-9]+]]
112; 32R2-NONAN:    nmadd.s $f0, $[[T0]], $f12, $f14
113
114; 32R2-NAN:      mtc1 $6, $[[T0:f[0-9]+]]
115; 32R2-NAN:      madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
116; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
117; 32R2-NAN:      sub.s  $f0, $[[T2]], $[[T1]]
118
119; 32R6-DAG:      mtc1 $6, $[[T0:f[0-9]+]]
120; 32R6-DAG:      mul.s $[[T1:f[0-9]+]], $f12, $f14
121; 32R6-DAG:      add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
122; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
123; 32R6-DAG:      sub.s $f0, $[[T2]], $[[T1]]
124
125; 64-NONAN:      nmadd.s $f0, $f14, $f12, $f13
126
127; 64-NAN:        madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
128; 64-NAN:        mtc1 $zero, $[[T1:f[0-9]+]]
129; 64-NAN:        sub.s  $f0, $[[T1]], $[[T0]]
130
131; 64R2-NONAN:    nmadd.s $f0, $f14, $f12, $f13
132
133; 64R2-NAN:      madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
134; 64R2-NAN:      mtc1 $zero, $[[T1:f[0-9]+]]
135; 64R2-NAN:      sub.s  $f0, $[[T1]], $[[T0]]
136
137; 64R6-DAG:      mul.s $[[T1:f[0-9]+]], $f12, $f13
138; 64R6-DAG:      add.s $[[T2:f[0-9]+]], $[[T1]], $f14
139; 64R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
140; 64R6-DAG:      sub.s $f0, $[[T2]], $[[T1]]
141
142  %mul = fmul float %a, %b
143  %add = fadd float %mul, %c
144  %sub = fsub float 0.000000e+00, %add
145  ret float %sub
146}
147
148define float @FOO3float(float %a, float %b, float %c) nounwind readnone {
149entry:
150; ALL-LABEL: FOO3float:
151
152; 32-DAG:        mtc1 $6, $[[T0:f[0-9]+]]
153; 32-DAG:        mul.s $[[T1:f[0-9]+]], $f12, $f14
154; 32-DAG:        sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
155; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
156; 32-DAG:        sub.s $f0, $[[T2]], $[[T1]]
157
158; 32R2-NONAN:    mtc1 $6, $[[T0:f[0-9]+]]
159; 32R2-NONAN:    nmsub.s $f0, $[[T0]], $f12, $f14
160
161; 32R2-NAN:      mtc1 $6, $[[T0:f[0-9]+]]
162; 32R2-NAN:      msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
163; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
164; 32R2-NAN:      sub.s  $f0, $[[T2]], $[[T1]]
165
166; 64-NAN:        msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
167; 64-NAN:        mtc1 $zero, $[[T1:f[0-9]+]]
168; 64-NAN:        sub.s  $f0, $[[T1]], $[[T0]]
169
170; 64-NONAN:      nmsub.s $f0, $f14, $f12, $f13
171
172; 64R2-NAN:      msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
173; 64R2-NAN:      mtc1 $zero, $[[T1:f[0-9]+]]
174; 64R2-NAN:      sub.s  $f0, $[[T1]], $[[T0]]
175
176; 64R6-DAG:      mul.s $[[T1:f[0-9]+]], $f12, $f13
177; 64R6-DAG:      sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
178; 64R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
179; 64R6-DAG:      sub.s $f0, $[[T2]], $[[T1]]
180
181  %mul = fmul float %a, %b
182  %sub = fsub float %mul, %c
183  %sub1 = fsub float 0.000000e+00, %sub
184  ret float %sub1
185}
186
187define double @FOO10double(double %a, double %b, double %c) nounwind readnone {
188entry:
189; ALL-LABEL: FOO10double:
190
191; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
192; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
193; 32-DAG:        add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
194; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
195; 32-DAG:        add.d $f0, $[[T1]], $[[T2]]
196
197; 32R2:          ldc1 $[[T0:f[0-9]+]], 16($sp)
198; 32R2:          madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
199; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
200; 32R2:          mthc1 $zero, $[[T2]]
201; 32R2:          add.d $f0, $[[T1]], $[[T2]]
202
203; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
204; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
205; 32R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
206; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
207; 32R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
208
209; 64-DAG:        madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
210; 64-DAG:        mtc1 $zero, $[[T1:f[0-9]+]]
211; 64-DAG:        add.d $f0, $[[T0]], $[[T1]]
212
213; 64R2:          madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
214; 64R2:          mtc1 $zero, $[[T1:f[0-9]+]]
215; 64R2:          add.d $f0, $[[T0]], $[[T1]]
216
217; 64R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f13
218; 64R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $f14
219; 64R6-DAG:      dmtc1 $zero, $[[T2:f[0-9]+]]
220; 64R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
221
222  %mul = fmul double %a, %b
223  %add = fadd double %mul, %c
224  %add1 = fadd double %add, 0.000000e+00
225  ret double %add1
226}
227
228define double @FOO11double(double %a, double %b, double %c) nounwind readnone {
229entry:
230; ALL-LABEL: FOO11double:
231
232; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
233; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
234; 32-DAG:        sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
235; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
236; 32-DAG:        add.d $f0, $[[T1]], $[[T2]]
237
238; 32R2:          ldc1 $[[T0:f[0-9]+]], 16($sp)
239; 32R2:          msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
240; 32R2:          mtc1 $zero, $[[T2:f[0-9]+]]
241; 32R2:          mthc1 $zero, $[[T2]]
242; 32R2:          add.d $f0, $[[T1]], $[[T2]]
243
244; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
245; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
246; 32R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
247; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
248; 32R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
249
250; 64-DAG:        msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
251; 64-DAG:        mtc1 $zero, $[[T1:f[0-9]+]]
252; 64-DAG:        add.d $f0, $[[T0]], $[[T1]]
253
254; 64R2:          msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
255; 64R2:          mtc1 $zero, $[[T1:f[0-9]+]]
256; 64R2:          add.d $f0, $[[T0]], $[[T1]]
257
258; 64R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f13
259; 64R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
260; 64R6-DAG:      dmtc1 $zero, $[[T2:f[0-9]+]]
261; 64R6-DAG:      add.d $f0, $[[T1]], $[[T2]]
262
263  %mul = fmul double %a, %b
264  %sub = fsub double %mul, %c
265  %add = fadd double %sub, 0.000000e+00
266  ret double %add
267}
268
269define double @FOO12double(double %a, double %b, double %c) nounwind readnone {
270entry:
271; ALL-LABEL: FOO12double:
272
273; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
274; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
275; 32-DAG:        add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
276; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
277; 32-DAG:        sub.d $f0, $[[T2]], $[[T1]]
278
279; 32R2-NONAN:    ldc1 $[[T0:f[0-9]+]], 16($sp)
280; 32R2-NONAN:    nmadd.d $f0, $[[T0]], $f12, $f14
281
282; 32R2-NAN:      ldc1 $[[T0:f[0-9]+]], 16($sp)
283; 32R2-NAN:      madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
284; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
285; 32R2-NAN:      mthc1 $zero, $[[T2]]
286; 32R2-NAN:      sub.d $f0, $[[T2]], $[[T1]]
287
288; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
289; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
290; 32R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
291; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
292; 32R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
293
294; 64-NONAN:      nmadd.d $f0, $f14, $f12, $f13
295
296; 64-NAN:        madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
297; 64-NAN:        mtc1 $zero, $[[T1:f[0-9]+]]
298; 64-NAN:        sub.d $f0, $[[T1]], $[[T0]]
299
300; 64R2-NONAN:    nmadd.d $f0, $f14, $f12, $f13
301
302; 64R2-NAN:      madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
303; 64R2-NAN:      mtc1 $zero, $[[T1:f[0-9]+]]
304; 64R2-NAN:      sub.d $f0, $[[T1]], $[[T0]]
305
306; 64R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f13
307; 64R6-DAG:      add.d $[[T2:f[0-9]+]], $[[T1]], $f14
308; 64R6-DAG:      dmtc1 $zero, $[[T2:f[0-9]+]]
309; 64R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
310
311  %mul = fmul double %a, %b
312  %add = fadd double %mul, %c
313  %sub = fsub double 0.000000e+00, %add
314  ret double %sub
315}
316
317define double @FOO13double(double %a, double %b, double %c) nounwind readnone {
318entry:
319; ALL-LABEL: FOO13double:
320
321; 32-DAG:        ldc1 $[[T0:f[0-9]+]], 16($sp)
322; 32-DAG:        mul.d $[[T1:f[0-9]+]], $f12, $f14
323; 32-DAG:        sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
324; 32-DAG:        mtc1 $zero, $[[T2:f[0-9]+]]
325; 32-DAG:        sub.d $f0, $[[T2]], $[[T1]]
326
327; 32R2-NONAN:    ldc1 $[[T0:f[0-9]+]], 16($sp)
328; 32R2-NONAN:    nmsub.d $f0, $[[T0]], $f12, $f14
329
330; 32R2-NAN:      ldc1 $[[T0:f[0-9]+]], 16($sp)
331; 32R2-NAN:      msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
332; 32R2-NAN:      mtc1 $zero, $[[T2:f[0-9]+]]
333; 32R2-NAN:      mthc1 $zero, $[[T2]]
334; 32R2-NAN:      sub.d $f0, $[[T2]], $[[T1]]
335
336; 32R6-DAG:      ldc1 $[[T0:f[0-9]+]], 16($sp)
337; 32R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f14
338; 32R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
339; 32R6-DAG:      mtc1 $zero, $[[T2:f[0-9]+]]
340; 32R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
341
342; 64-NONAN:      nmsub.d $f0, $f14, $f12, $f13
343
344; 64-NAN:        msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
345; 64-NAN:        mtc1 $zero, $[[T1:f[0-9]+]]
346; 64-NAN:        sub.d $f0, $[[T1]], $[[T0]]
347
348; 64R2-NONAN:    nmsub.d $f0, $f14, $f12, $f13
349
350; 64R2-NAN:      msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
351; 64R2-NAN:      mtc1 $zero, $[[T1:f[0-9]+]]
352; 64R2-NAN:      sub.d $f0, $[[T1]], $[[T0]]
353
354; 64R6-DAG:      mul.d $[[T1:f[0-9]+]], $f12, $f13
355; 64R6-DAG:      sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
356; 64R6-DAG:      dmtc1 $zero, $[[T2:f[0-9]+]]
357; 64R6-DAG:      sub.d $f0, $[[T2]], $[[T1]]
358
359  %mul = fmul double %a, %b
360  %sub = fsub double %mul, %c
361  %sub1 = fsub double 0.000000e+00, %sub
362  ret double %sub1
363}
364