| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 175 return dreg(0); in CallDouble()
618 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1)); in DoRuntimeCall()
619 int64_t result = target(dreg(0), dreg(1)); in DoRuntimeCall()
633 TraceSim("Argument: %f\n", dreg(0)); in DoRuntimeCall()
634 double result = target(dreg(0)); in DoRuntimeCall()
648 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1)); in DoRuntimeCall()
649 double result = target(dreg(0), dreg(1)); in DoRuntimeCall()
663 TraceSim("Arguments: %f, %d\n", dreg(0), wreg(0)); in DoRuntimeCall()
664 double result = target(dreg(0), wreg(0)); in DoRuntimeCall()
1607 case STR_d: MemoryWrite<double>(address, dreg(srcdst)); break; in LoadStoreHelper()
[all …]
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| D | simulator-arm64.h | 427 double dreg(unsigned code) const {
438 case kDRegSizeInBits: return dreg(code);
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| /external/v8/src/arm/ |
| D | simulator-arm.h | 141 void set_dw_register(int dreg, const int* dbl);
144 void get_d_register(int dreg, uint64_t* value);
145 void set_d_register(int dreg, const uint64_t* value);
146 void get_d_register(int dreg, uint32_t* value);
147 void set_d_register(int dreg, const uint32_t* value);
156 void set_d_register_from_double(int dreg, const double& dbl) { in set_d_register_from_double() argument
157 SetVFPRegister<double, 2>(dreg, dbl); in set_d_register_from_double()
160 double get_double_from_d_register(int dreg) { in get_double_from_d_register() argument
161 return GetFromVFPRegister<double, 2>(dreg); in get_double_from_d_register()
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| D | simulator-arm.cc | 910 void Simulator::set_dw_register(int dreg, const int* dbl) { in set_dw_register() argument
911 DCHECK((dreg >= 0) && (dreg < num_d_registers)); in set_dw_register()
912 registers_[dreg] = dbl[0]; in set_dw_register()
913 registers_[dreg + 1] = dbl[1]; in set_dw_register()
917 void Simulator::get_d_register(int dreg, uint64_t* value) { in get_d_register() argument
918 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters())); in get_d_register()
919 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value)); in get_d_register()
923 void Simulator::set_d_register(int dreg, const uint64_t* value) { in set_d_register() argument
924 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters())); in set_d_register()
925 memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value)); in set_d_register()
[all …]
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 2859 UInt dreg = get_neon_d_regno(theInstr); in dis_neon_vext() local
2867 putQReg(dreg, triop(Iop_SliceV128, /*hiV128*/getQReg(mreg), in dis_neon_vext()
2870 putDRegI64(dreg, triop(Iop_Slice64, /*hiI64*/getDRegI64(mreg), in dis_neon_vext()
2873 DIP("vext.8 %c%d, %c%d, %c%d, #%d\n", reg_t, dreg, reg_t, nreg, in dis_neon_vext()
2908 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); in dis_neon_vtb() local
2920 if (dreg >= 0x100 || mreg >= 0x100 || nreg >= 0x100) in dis_neon_vtb()
2966 getDRegI64(dreg), in dis_neon_vtb()
2972 putDRegI64(dreg, mkexpr(old_res), condT); in dis_neon_vtb()
2973 DIP("vtb%c.8 d%u, {", op ? 'x' : 'l', dreg); in dis_neon_vtb()
2988 UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); in dis_neon_vdup() local
[all …]
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| D | host_arm_isel.c | 3749 HReg dreg = iselNeon64Expr(env, triop->arg1); in iselNeon64Expr_wrk() local
3764 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False)); in iselNeon64Expr_wrk()
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 1138 case STR_d: Memory::Write<double>(address, dreg(srcdst)); break; in LoadStoreHelper()
1254 Memory::Write<double>(address, dreg(rt)); in LoadStorePairHelper()
1255 Memory::Write<double>(address2, dreg(rt2)); in LoadStorePairHelper()
1977 case FCVTAS_wd: set_wreg(dst, FPToInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1978 case FCVTAS_xd: set_xreg(dst, FPToInt64(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1981 case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1982 case FCVTAU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1990 set_wreg(dst, FPToInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
1993 set_xreg(dst, FPToInt64(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
2002 set_wreg(dst, FPToUInt32(dreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
[all …]
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| D | simulator-a64.h | 997 double dreg(unsigned code) const { in dreg() function
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| /external/vixl/examples/ |
| D | add3-double.cc | 69 printf("%f + %f + %f = %f\n", a, b, c, simulator.dreg(0)); in main()
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| D | add4-double.cc | 79 printf("%ld + %f + %ld + %f = %f\n", a, b, c, d, simulator.dreg(0)); in main()
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| /external/v8/test/cctest/ |
| D | test-utils-arm64.h | 89 inline double dreg(unsigned code) const { in dreg() function
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| D | test-utils-arm64.cc | 142 return EqualFP64(expected, core, core->dreg(fpreg.code())); in EqualFP64()
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| /external/vixl/test/ |
| D | test-utils-a64.h | 110 inline double dreg(unsigned code) const { in dreg() function
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| D | test-utils-a64.cc | 174 return EqualFP64(expected, core, core->dreg(fpreg.code())); in EqualFP64()
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| /external/vixl/test/examples/ |
| D | test-examples.cc | 334 assert(regs.dreg(0) == Add3DoubleC(A, B, C)); \
360 assert(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
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| /external/v8/src/mips/ |
| D | simulator-mips.h | 161 void set_dw_register(int dreg, const int* dbl);
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| /external/v8/src/mips64/ |
| D | simulator-mips64.h | 191 void set_dw_register(int dreg, const int* dbl);
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| /external/llvm/test/CodeGen/ARM/ |
| D | vector-load.ll | 227 ; Make sure we don't break smaller-than-dreg extloads.
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| /external/hyphenation-patterns/nb/ |
| D | hyph-nb.pat.txt | 4902 9dreg.
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| /external/hyphenation-patterns/nn/ |
| D | hyph-nn.pat.txt | 4902 9dreg.
|