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Searched refs:dreg_bits (Results 1 – 9 of 9) sorted by relevance

/external/vixl/test/examples/
Dtest-examples.cc135 saved_dregs[0] = simulator.dreg_bits(8); \
136 saved_dregs[1] = simulator.dreg_bits(9); \
137 saved_dregs[2] = simulator.dreg_bits(10); \
138 saved_dregs[3] = simulator.dreg_bits(11); \
139 saved_dregs[4] = simulator.dreg_bits(12); \
140 saved_dregs[5] = simulator.dreg_bits(13); \
141 saved_dregs[6] = simulator.dreg_bits(14); \
142 saved_dregs[7] = simulator.dreg_bits(15); \
161 assert(saved_dregs[0] == simulator.dreg_bits(8)); \
162 assert(saved_dregs[1] == simulator.dreg_bits(9)); \
[all …]
/external/v8/test/cctest/
Dtest-utils-arm64.h84 inline uint64_t dreg_bits(unsigned code) const { in dreg_bits() function
90 return rawbits_to_double(dreg_bits(code)); in dreg()
Dtest-utils-arm64.cc127 uint64_t result_64 = core->dreg_bits(fpreg.code()); in EqualFP32()
200 uint64_t a_bits = a->dreg_bits(i); in EqualRegisters()
201 uint64_t b_bits = b->dreg_bits(i); in EqualRegisters()
/external/vixl/test/
Dtest-utils-a64.h105 inline uint64_t dreg_bits(unsigned code) const { in dreg_bits() function
111 return rawbits_to_double(dreg_bits(code)); in dreg()
Dtest-utils-a64.cc159 uint64_t result_64 = core->dreg_bits(fpreg.code()); in EqualFP32()
232 uint64_t a_bits = a->dreg_bits(i); in EqualRegisters()
233 uint64_t b_bits = b->dreg_bits(i); in EqualRegisters()
/external/v8/src/arm64/
Dsimulator-arm64.h431 uint64_t dreg_bits(unsigned code) const {
Dsimulator-arm64.cc242 dreg_bits(fpregister_list.PopLowestIndex().code()); in CheckPCSComplianceAndRun()
258 dreg_bits(fpregister_list.PopLowestIndex().code())); in CheckPCSComplianceAndRun()
2271 case FMOV_xd: set_xreg(dst, dreg_bits(src)); break; in VisitFPIntegerConvert()
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1001 uint64_t dreg_bits(unsigned code) const { in dreg_bits() function
Dsimulator-a64.cc2048 case FMOV_xd: set_xreg(dst, dreg_bits(src)); break; in VisitFPIntegerConvert()