| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(SU->getInstr())) in isResourceAvailable()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(SU->getInstr()); in reserveResources()
124 DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
245 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
277 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
[all …]
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| D | HexagonVLIWPacketizer.cpp | 561 if (PacketSU->getInstr()->getDesc().mayStore() || in CanPromoteToNewValueStore()
564 PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe || in CanPromoteToNewValueStore()
565 PacketSU->getInstr()->getOpcode() == Hexagon::L2_deallocframe) in CanPromoteToNewValueStore()
661 MachineInstr* TempMI = TempSU->getInstr(); in CanPromoteToNewValueStore()
675 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), in CanPromoteToNewValueStore()
725 MachineInstr *PacketMI = PacketSU->getInstr(); in CanPromoteToNewValue()
991 MachineInstr *I = SUI->getInstr(); in isLegalToPacketizeTogether()
992 MachineInstr *J = SUJ->getInstr(); in isLegalToPacketizeTogether()
1099 if (PacketSU->getInstr()->getDesc().isCall()) { in isLegalToPacketizeTogether()
1111 if (PacketSU->getInstr()->getDesc().mayStore() || in isLegalToPacketizeTogether()
[all …]
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| /external/llvm/lib/Target/R600/ |
| D | R600MachineScheduler.cpp | 163 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
164 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
198 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
223 MachineInstr *MI = SU->getInstr(); in getAluKind()
297 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
326 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
328 && (!AnyALU || !TII->isVectorOnly(SU->getInstr())) in PopInst()
398 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
447 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
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| D | R600Packetizer.cpp | 189 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr(); in isLegalToPacketizeTogether()
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| D | SILoadStoreOptimizer.cpp | 291 return Read2.getInstr(); in mergeRead2Pair()
358 return Write2.getInstr(); in mergeWrite2Pair()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
280 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
283 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
296 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
316 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
322 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
377 const MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
401 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
415 MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
606 isGlobalMemoryObject(AA, SUb->getInstr())) in iterateChainSucc()
[all …]
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| D | MachineScheduler.cpp | 690 MachineInstr *MI = SU->getInstr(); in schedule()
982 << *SU->getInstr()); in updatePressureDiffs()
987 = LI.Query(LIS->getInstructionIndex(SU->getInstr())); in updatePressureDiffs()
1158 LI.Query(LIS->getInstructionIndex(UI->SU->getInstr())); in computeCyclicCriticalPath()
1190 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1273 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) in clusterNeighboringLoads()
1288 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength) in clusterNeighboringLoads()
1319 if (!SU->getInstr()->mayLoad()) in apply()
1363 MachineInstr *Branch = DAG->ExitSU.getInstr(); in apply()
1369 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch)) in apply()
[all …]
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| D | SlotIndexes.cpp | 184 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
222 if (itr->getInstr()) { in dump()
223 dbgs() << *itr->getInstr(); in dump()
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| D | CriticalAntiDepBreaker.cpp | 442 MISUnitMap[SU->getInstr()] = SU; in BreakAntiDependencies()
463 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
574 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
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| D | DFAPacketizer.cpp | 170 MIToSUnit[SU->getInstr()] = SU; in PacketizeMIs()
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| D | AggressiveAntiDepBreaker.cpp | 748 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(), in BreakAntiDependencies()
767 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
812 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr; in BreakAntiDependencies()
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| D | PostRASchedulerList.cpp | 660 BB->splice(RegionEnd, BB, SU->getInstr()); in EmitSchedule()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 38 MachineInstr *MI = SU->getInstr(); in getHazardType()
85 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
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| D | Thumb2ITBlockPass.cpp | 191 MachineBasicBlock::iterator InsertPos = MIB.getInstr(); in InsertITInstructions()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SlotIndexes.h | 46 MachineInstr* getInstr() const { return mi; } in getInstr() function
424 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
433 if (I->getInstr())
616 assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
631 assert(miEntry->getInstr() == mi &&
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| D | ScheduleDAGInstrs.h | 174 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
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| D | ScheduleDAG.h | 406 MachineInstr *getInstr() const {
585 if (SU->isInstr()) return &SU->getInstr()->getDesc();
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| D | MachineInstrBuilder.h | 63 MachineInstr *getInstr() const { return MI; } in getInstr() function
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 451 .getInstr(); in loadImmediate()
455 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
463 .getInstr(); in loadImmediate()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 328 MachineInstr *MI = SU->getInstr(); in getHazardType()
386 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
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| /external/llvm/include/llvm/Analysis/ |
| D | LoopAccessAnalysis.h | 56 const Instruction *getInstr() const { return Instr; } in getInstr() function
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| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 423 .getInstr(); in adjustCallSequence()
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| D | X86FloatingPoint.cpp | 839 .getInstr(); in freeStackSlotBefore()
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| /external/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 70 if (const Instruction *I = Message.getInstr()) in emitAnalysis()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 219 R.getInstr()) {} in VectorizationReport()
|