| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); in spillCalleeSavedRegisters()
266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
307 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); in restoreCalleeSavedRegisters()
320 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| D | HexagonVLIWPacketizer.cpp | 339 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg); in IsCallDependent()
610 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc); in CanPromoteToNewValueStore()
622 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst); in CanPromoteToNewValueStore()
1169 RC = QRI->getMinimalPhysRegClass(DepReg); in isLegalToPacketizeTogether()
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| D | HexagonExpandCondsets.cpp | 655 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); in getCondTfrOpcode()
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| D | HexagonInstrInfo.cpp | 1110 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); in DefinesPredicate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 113 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize(); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 244 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; in expandCopyACC()
590 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/R600/ |
| D | SIInsertWaits.cpp | 160 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); in getHwCounts()
233 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); in getRegInterval()
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| D | SIISelLowering.cpp | 553 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); in LowerFormalArguments()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece()
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| /external/llvm/lib/CodeGen/ |
| D | PrologEpilogInserter.cpp | 335 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters()
404 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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| D | StackMaps.cpp | 136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
231 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); in createLiveOutReg()
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| D | TargetRegisterInfo.cpp | 112 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
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| D | AggressiveAntiDepBreaker.cpp | 614 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 318 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1416 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
1462 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1494 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 583 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()
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| D | ScheduleDAGSDNodes.cpp | 134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
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| D | InstrEmitter.cpp | 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
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| D | ScheduleDAGRRList.cpp | 1451 TRI->getMinimalPhysRegClass(Reg, VT); in PickNodeToScheduleBottomUp()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1541 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1686 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 253 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
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