| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGPrinter.cpp | 71 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget()
131 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
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| D | InstrEmitter.cpp | 115 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
125 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
127 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg()
198 User->getOperand(2).getResNo() == ResNo) { in getDstOfOnlyCopyToRegUse()
247 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters()
288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR()
670 SDValue Op = SDValue(Node, SD->getResNo()); in EmitDbgValue()
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| D | SDNodeDbgValue.h | 96 unsigned getResNo() const { assert (kind==SDNODE); return u.s.ResNo; } in getResNo() function
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| D | ResourcePriorityQueue.cpp | 134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta()
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
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| D | SelectionDAGDumper.cpp | 594 if (unsigned RN = N->getOperand(i).getResNo()) in DumpNodesr()
664 if (unsigned RN = getOperand(i).getResNo()) in print()
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| D | SelectionDAG.cpp | 389 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
399 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
2071 if (Op.getResNo() != 1) in computeKnownBits()
2197 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
2496 if (Op.getResNo() != 1) in ComputeNumSignBits()
2603 if (Op.getResNo() == 0) { in ComputeNumSignBits()
5966 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && in ReplaceAllUsesWith()
6050 setRoot(SDValue(To, getRoot().getResNo())); in ReplaceAllUsesWith()
6078 const SDValue &ToOp = To[Use.getResNo()]; in ReplaceAllUsesWith()
6090 setRoot(SDValue(To[getRoot().getResNo()])); in ReplaceAllUsesWith()
[all …]
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| D | ScheduleDAGSDNodes.cpp | 121 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency()
636 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
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| D | SelectionDAGBuilder.cpp | 788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), in getCopyToRegs()
1012 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(), in resolveDanglingDebugInfo()
1244 SDValue(RetOp.getNode(), RetOp.getResNo() + i), in visitRet()
1282 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet()
2960 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), in visitSelect()
2963 TrueVal.getResNo() + i), in visitSelect()
2965 FalseVal.getResNo() + i)); in visitSelect()
3328 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
3334 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); in visitInsertValue()
3339 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
[all …]
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| D | LegalizeVectorOps.cpp | 181 return Result.getValue(Op.getResNo()); in TranslateLegalizeResults()
621 return (Op.getResNo() ? NewChain : Value); in ExpandLoad()
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| D | ScheduleDAGFast.cpp | 232 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| D | LegalizeTypes.cpp | 92 if (UI.getUse().getResNo() == i) in PerformExpensiveChecks()
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| D | ScheduleDAGRRList.cpp | 956 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| D | SelectionDAGISel.cpp | 1853 if (Use.getResNo() == FlagResNo) in findGlueUse()
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| D | DAGCombiner.cpp | 5366 if (UI.getUse().getResNo() != N0.getResNo()) in ExtendUsesToFormExtLoad()
5401 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
6759 return Elt.getOperand(Elt.getResNo()).getNode(); in getBuildPairElt()
9578 if (UI.getUse().getResNo() != 0) in SliceUpLoad()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcher.cpp | 393 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl()
396 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
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| D | DAGISelMatcherOpt.cpp | 53 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes()
436 CTM->getResNo() != 0 || in FactorNodes()
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| D | DAGISelMatcherEmitter.cpp | 363 assert(cast<CheckTypeMatcher>(N)->getResNo() == 0 && in EmitMatcher()
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| D | DAGISelMatcher.h | 538 unsigned getResNo() const { return ResNo; } in getResNo() function
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 115 unsigned getResNo() const { return ResNo; }
204 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
264 unsigned getResNo() const { return Val.getResNo(); }
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1107 if (N.getResNo() != 0) break; in MatchAddressRecursively()
1891 if (FlagUI.getUse().getResNo() != 1) continue; in HasNoSignedComparisonUses()
1947 if (StoredVal.getResNo() != 0) return false; in isLoadIncOrDecStore()
2001 if (UI.getUse().getResNo() != 0) in isLoadIncOrDecStore()
2634 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) && in Select()
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| D | X86ISelLowering.cpp | 12516 if (Op.getResNo() != 0 || NeedOF || NeedCF) { in EmitTest()
13377 if (Op.getResNo() == 1 && in isX86LogicalCmp()
13391 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) in isX86LogicalCmp()
14004 Cond.getOperand(0).getResNo() == 1 && in LowerBRCOND()
19345 if (Op.getResNo() == 0) in computeKnownBitsForTargetNode()
20539 if (UI.getUse().getResNo() != InputVector.getResNo()) in PerformEXTRACT_VECTOR_ELTCombine()
21413 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0) in checkBoolTestSetCCCombine()
23250 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 && in PerformSExtCombine()
23363 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 && in PerformZExtCombine()
23546 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo()); in PerformSETCCCombine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) in selectMADD()
487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) in selectMSUB()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3255 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) && in LowerBR_CC()
3771 if (CCVal.getResNo() == 1 && in LowerSELECT()
8094 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result. in performPostLD1Combine()
8107 || UI.getUse().getResNo() != Addr.getResNo()) in performPostLD1Combine()
8174 UI.getUse().getResNo() != Addr.getResNo()) in performNEONPostLDSTCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3313 if (Cond.getResNo() == 1 && in LowerSELECT()
8521 Op0.getResNo() == 0 && Op1.getResNo() == 1) in PerformVMOVDRRCombine()
8767 UI.getUse().getResNo() != Addr.getResNo()) in CombineBaseUpdate()
9002 if (UI.getUse().getResNo() == NumVecs) in CombineVLDDUP()
9026 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP()
10403 if (Op.getResNo() == 0) in computeKnownBitsForTargetNode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1861 if (Op.getResNo() == 1) { in computeKnownBitsForTargetNode()
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