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Searched refs:getSubReg (Results 1 – 25 of 70) sorted by relevance

123

/external/mesa3d/src/gallium/drivers/radeon/
DR600ExpandSpecialInstrs.cpp106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
646 SrcSubReg = MOSrc.getSubReg(); in getNextRewritableSource()
650 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
695 SrcSubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
701 if (MODef.getSubReg()) in getNextRewritableSource()
744 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
752 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
822 if ((SrcSubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
832 return MODef.getSubReg() == 0; in getNextRewritableSource()
954 TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg()); in optimizeUncoalescableCopy()
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DCalcSpillWeights.cpp49 sub = mi->getOperand(0).getSubReg(); in copyHint()
51 hsub = mi->getOperand(1).getSubReg(); in copyHint()
53 sub = mi->getOperand(1).getSubReg(); in copyHint()
55 hsub = mi->getOperand(0).getSubReg(); in copyHint()
DTargetRegisterInfo.cpp194 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
233 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
242 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
252 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
253 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
DTargetInstrInfo.cpp140 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstruction()
141 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstruction()
142 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); in commuteInstruction()
353 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
426 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
576 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
895 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
919 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
942 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
945 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
DMachineInstr.cpp72 if (SubIdx && getSubReg()) in substVirtReg()
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
81 if (getSubReg()) { in substPhysReg()
82 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
196 getSubReg() == Other.getSubReg(); in isIdenticalTo()
238 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
283 OS << PrintReg(getReg(), TRI, getSubReg()); in print()
299 if (isUndef() && getSubReg()) in print()
1099 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect()
1160 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister()
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DVirtRegMap.cpp261 unsigned SubReg = SR.getSubReg(); in addMBBLiveIns()
367 if (MO.getSubReg()) { in rewrite()
392 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); in rewrite()
DOptimizePHIs.cpp111 !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
112 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
DRegAllocFast.cpp677 if (!MO.getSubReg()) { in setPhysReg()
683 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
714 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
752 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { in handleThroughOperands()
905 CopyDstSub = MI->getOperand(0).getSubReg(); in AllocateBasicBlock()
906 CopySrcSub = MI->getOperand(1).getSubReg(); in AllocateBasicBlock()
938 if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) in AllocateBasicBlock()
DExpandPostRAPseudos.cpp89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/llvm/lib/Target/R600/
DSIFoldOperands.cpp120 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
195 OpToFold.getSubReg())) in runOnMachineFunction()
207 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in runOnMachineFunction()
224 if (UseOp.getSubReg()) { in runOnMachineFunction()
228 if (UseOp.getSubReg() == AMDGPU::sub0) { in runOnMachineFunction()
231 assert(UseOp.getSubReg() == AMDGPU::sub1); in runOnMachineFunction()
DSIFixSGPRCopies.cpp152 I->getOperand(0).getSubReg())); in inferRegClassFromUses()
175 Def->getOperand(1).getSubReg()); in inferRegClassFromDef()
184 unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); in isVGPRToSGPRCopy()
231 = inferRegClassFromDef(TRI, MRI, Reg, Op.getSubReg()); in runOnMachineFunction()
237 MI.getOperand(0).getSubReg()); in runOnMachineFunction()
DR600ExpandSpecialInstrs.cpp187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIPrepareScratchRegs.cpp152 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in runOnMachineFunction()
153 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in runOnMachineFunction()
154 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in runOnMachineFunction()
155 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in runOnMachineFunction()
DSIInstrInfo.cpp420 get(Opcode), RI.getSubReg(DestReg, SubIdx)); in copyPhysReg()
422 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); in copyPhysReg()
679 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
680 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo()
704 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
705 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
721 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
724 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
733 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
734 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
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/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp141 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
143 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
145 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
147 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
149 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp181 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
182 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
193 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
194 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp448 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { in copyPhysReg()
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg, in copyPhysReg()
454 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg, in copyPhysReg()
456 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg, in copyPhysReg()
597 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
598 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
599 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
600 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
602 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi) in expandPostRAPseudo()
605 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo) in expandPostRAPseudo()
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DHexagonSplitConst32AndConst64.cpp145 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
146 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
DHexagonHardwareLoops.cpp257 unsigned getSubReg() const { in getSubReg() function in __anonfb58bf460111::CountValue
756 SR = Start->getSubReg(); in computeCount()
759 SR = End->getSubReg(); in computeCount()
774 DistSR = End->getSubReg(); in computeCount()
784 SubIB.addReg(End->getReg(), 0, End->getSubReg()) in computeCount()
785 .addReg(Start->getReg(), 0, Start->getSubReg()); in computeCount()
788 .addReg(Start->getReg(), 0, Start->getSubReg()); in computeCount()
790 SubIB.addReg(End->getReg(), 0, End->getSubReg()) in computeCount()
1079 .addReg(TripCount->getReg(), 0, TripCount->getSubReg()); in convertToHardwareLoop()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp186 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); in processBlock()
187 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg(); in processBlock()
188 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg(); in processBlock()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp360 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
361 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
362 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
363 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
365 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
366 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
367 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
368 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
371 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
372 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64()
583 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
604 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
DMipsSEFrameLowering.cpp192 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
193 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
249 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
250 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC()
433 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
435 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()

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