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/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_fp.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
5 declare float @llvm.hexagon.F2.sfadd(float, float)
7 %z = call float @llvm.hexagon.F2.sfadd(float %a, float %b)
13 declare i32 @llvm.hexagon.F2.sfclass(float, i32)
15 %z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0)
20 declare i32 @llvm.hexagon.F2.dfclass(double, i32)
22 %z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0)
28 declare i32 @llvm.hexagon.F2.sfcmpge(float, float)
30 %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b)
35 declare i32 @llvm.hexagon.F2.sfcmpuo(float, float)
[all …]
Dxtype_bit.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i32 @llvm.hexagon.S2.clbp(i64)
7 %z = call i32 @llvm.hexagon.S2.clbp(i64 %a)
12 declare i32 @llvm.hexagon.S2.cl0p(i64)
14 %z = call i32 @llvm.hexagon.S2.cl0p(i64 %a)
19 declare i32 @llvm.hexagon.S2.cl1p(i64)
21 %z = call i32 @llvm.hexagon.S2.cl1p(i64 %a)
26 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
28 %z = call i32 @llvm.hexagon.S4.clbpnorm(i64 %a)
33 declare i32 @llvm.hexagon.S4.clbpaddi(i64, i32)
[all …]
Dxtype_pred.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32)
7 %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
12 declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
14 %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
19 declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
21 %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
26 declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
28 %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
33 declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32)
[all …]
Dxtype_perm.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i32 @llvm.hexagon.A2.sat(i64)
7 %z = call i32 @llvm.hexagon.A2.sat(i64 %a)
12 declare i32 @llvm.hexagon.A2.sath(i32)
14 %z = call i32 @llvm.hexagon.A2.sath(i32 %a)
19 declare i32 @llvm.hexagon.A2.satuh(i32)
21 %z = call i32 @llvm.hexagon.A2.satuh(i32 %a)
26 declare i32 @llvm.hexagon.A2.satub(i32)
28 %z = call i32 @llvm.hexagon.A2.satub(i32 %a)
33 declare i32 @llvm.hexagon.A2.satb(i32)
[all …]
Dxtype_alu.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
5 declare i64 @llvm.hexagon.A2.absp(i64)
7 %z = call i64 @llvm.hexagon.A2.absp(i64 %a)
13 declare i32 @llvm.hexagon.A2.abs(i32)
15 %z = call i32 @llvm.hexagon.A2.abs(i32 %a)
20 declare i32 @llvm.hexagon.A2.abssat(i32)
22 %z = call i32 @llvm.hexagon.A2.abssat(i32 %a)
28 declare i32 @llvm.hexagon.S4.addaddi(i32, i32, i32)
30 %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
35 declare i32 @llvm.hexagon.S4.subaddi(i32, i32, i32)
[all …]
Dalu32_alu.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i32 @llvm.hexagon.A2.addi(i32, i32)
7 %z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
12 declare i32 @llvm.hexagon.A2.add(i32, i32)
14 %z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
19 declare i32 @llvm.hexagon.A2.addsat(i32, i32)
21 %z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
27 declare i32 @llvm.hexagon.A2.and(i32, i32)
29 %z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
34 declare i32 @llvm.hexagon.A2.or(i32, i32)
[all …]
Dxtype_complex.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i64 @llvm.hexagon.S4.vxaddsubh(i64, i64)
7 %z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b)
12 declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64)
14 %z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b)
19 declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64)
21 %z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b)
26 declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64)
28 %z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b)
34 declare i64 @llvm.hexagon.S4.vxaddsubw(i64, i64)
[all …]
Dxtype_shift.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
7 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
12 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
14 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
19 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
21 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
26 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
28 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
33 declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
[all …]
Dxtype_mpy.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
5 declare i32 @llvm.hexagon.M4.mpyrr.addi(i32, i32, i32)
7 %z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b)
12 declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32)
14 %z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0)
19 declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32)
21 %z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b)
26 declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32)
28 %z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0)
33 declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32)
[all …]
Dcr.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s
5 declare i32 @llvm.hexagon.C4.fastcorner9(i32, i32)
7 %z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
12 declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
14 %z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
20 declare i32 @llvm.hexagon.C2.any8(i32)
22 %z = call i32@llvm.hexagon.C2.any8(i32 %a)
27 declare i32 @llvm.hexagon.C2.all8(i32)
29 %z = call i32@llvm.hexagon.C2.all8(i32 %a)
36 declare i32 @llvm.hexagon.C2.and(i32, i32)
[all …]
Dalu32_perm.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
5 declare i64 @llvm.hexagon.A4.combineri(i32, i32)
7 %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
12 declare i64 @llvm.hexagon.A4.combineir(i32, i32)
14 %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
19 declare i64 @llvm.hexagon.A2.combineii(i32, i32)
21 %z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
26 declare i32 @llvm.hexagon.A2.combine.hh(i32, i32)
28 %z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b)
33 declare i32 @llvm.hexagon.A2.combine.hl(i32, i32)
[all …]
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-shift-imm.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
2 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
3 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
4 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
5 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
6 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
17 target triple = "hexagon"
21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
22 %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
23 %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
[all …]
Dvect-vshifts.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
7 target triple = "hexagon"
24 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
26 %11 = tail call i64 @llvm.hexagon.A2.combinew(i32 -1, i32 -1)
40 %14 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %13, i32 31)
45 %17 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %14, i64 %16)
47 %19 = tail call i64 @llvm.hexagon.C2.vmux(i32 %17, i64 %13, i64 %18)
48 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
69 %25 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %24, i32 31)
74 %28 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %25, i64 %27)
[all …]
Dvect-truncate.ll1 ; RUN: llc -march=hexagon < %s
6 target triple = "hexagon-unknown-linux-gnu"
26 %p_25 = call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 undef)
42 declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) nounwind readnone
/external/llvm/test/CodeGen/Hexagon/
Dcirc_ldd_bug.ll3 target triple = "hexagon"
17 declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
32 %4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8)
36 %6 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 0, i64 %1, i64 %5)
74 %11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8)
80 %14 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %6, i64 %12, i64 %13)
88 %16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8)
94 %19 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %15, i64 %17, i64 %18)
102 %21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8)
108 %24 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %20, i64 %22, i64 %23)
[all …]
Dbrev_ld.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
19 target triple = "hexagon"
33 %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl)
39 declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind
53 %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl)
59 declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind
73 %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl)
79 declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind
93 %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl)
[all …]
Dbrev_st.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
18 target triple = "hexagon"
30 %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl)
36 declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind
48 %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl)
54 declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind
66 %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
72 declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind
84 %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl)
[all …]
Dcirc_ld.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s
18 target triple = "hexagon"
30 %1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1)
35 declare i8* @llvm.hexagon.circ.ldb(i8*, i8*, i32, i32) nounwind
49 %2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8)
55 declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
68 %2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2)
74 declare i8* @llvm.hexagon.circ.ldh(i8*, i8*, i32, i32) nounwind
86 %1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1)
91 declare i8* @llvm.hexagon.circ.ldub(i8*, i8*, i32, i32) nounwind
[all …]
Dcirc_st.ll1 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s
17 target triple = "hexagon"
28 %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1)
33 declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind
45 %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8)
51 declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind
62 %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
68 declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind
79 %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2)
85 declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind
[all …]
Dvaddh.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
11 %2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1)
16 declare i32 @llvm.hexagon.A2.svaddh(i32, i32) nounwind readnone
Dcombine.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
12 %2 = call i64 @llvm.hexagon.A2.combinew(i32 %0, i32 %conv)
17 declare i64 @llvm.hexagon.A2.combinew(i32, i32) nounwind readnone
Dremove_lsr.ll2 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
44 %0 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %val.021)
48 %3 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv3, i32 %1, i32 %2)
55 %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7)
74 declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) nounwind readnone
76 declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) nounwind readnone
Dcirc_ldw.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
13 %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 83886144, i32 -4)
18 declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) nounwind
/external/llvm/test/Object/
Dobjdump-relocations.test9 RUN: llvm-objdump -r %p/Inputs/trivial-object-test.elf-hexagon \
10 RUN: | FileCheck %s -check-prefix ELF-hexagon
39 ELF-hexagon: .text
40 ELF-hexagon: R_HEX_GOTREL_HI16 .main
41 ELF-hexagon: R_HEX_GOTREL_LO16 .main
42 ELF-hexagon: R_HEX_HI16 puts
43 ELF-hexagon: R_HEX_LO16 puts
44 ELF-hexagon: R_HEX_B15_PCREL testf
45 ELF-hexagon: R_HEX_B22_PCREL puts
/external/llvm/test/MC/Hexagon/
Dbasic.ll1 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
4 ; OBJ: Format: ELF32-hexagon
5 ; OBJ: Arch: hexagon

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