| /external/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 26 static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5, ARM_ShifterType &sh… in DecodeImmShift() argument
34 return imm5; in DecodeImmShift()
37 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
40 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
42 if (imm5 == 0) in DecodeImmShift()
50 return imm5; in DecodeImmShift()
72 static inline uint32_t DecodeImmShift(const ARM_ShifterType shift_t, const uint32_t imm5) in DecodeImmShift() argument
75 return DecodeImmShift(shift_t, imm5, dont_care); in DecodeImmShift()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 197 // t_addrmode_is4 := reg + imm5 * 4
209 // t_addrmode_is2 := reg + imm5 * 2
221 // t_addrmode_is1 := reg + imm5
592 // Loads: reg/reg and reg/imm5
604 def i : // reg/imm5
610 // Stores: reg/reg and reg/imm5
621 def i : // reg/imm5
913 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
915 "asr", "\t$Rd, $Rm, $imm5",
916 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
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| D | ARMInstrFormats.td | 1168 let Inst{10-6} = addr{7-3}; // imm5
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| D | ARMInstrInfo.td | 510 // {4-0} imm5 shift amount.
511 // asr #32 encoded as imm5 == 0.
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| D | ARMInstrThumb2.td | 35 // {4-0} imm5 shift amount.
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 3195 UInt imm5 = INSN(20,16); in dis_ARM64_data_processing_register() local
3209 assign(argR, mkU64(imm5)); in dis_ARM64_data_processing_register()
3212 assign(argR, mkU32(imm5)); in dis_ARM64_data_processing_register()
3218 imm5, nzcv, nameCC(cond)); in dis_ARM64_data_processing_register()
7629 IRExpr* srcV, UInt imm5 ) in handle_DUP_VEC_ELEM() argument
7635 if (imm5 & 1) { in handle_DUP_VEC_ELEM()
7636 *laneNo = (imm5 >> 1) & 15; in handle_DUP_VEC_ELEM()
7640 else if (imm5 & 2) { in handle_DUP_VEC_ELEM()
7641 *laneNo = (imm5 >> 2) & 7; in handle_DUP_VEC_ELEM()
7645 else if (imm5 & 4) { in handle_DUP_VEC_ELEM()
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| D | guest_arm_toIR.c | 1599 UInt imm5 ) /* saturation ceiling */ in armUnsignedSatQ() argument
1601 UInt ceil = (1 << imm5) - 1; // (2^imm5)-1 in armUnsignedSatQ()
1641 UInt imm5, /* saturation ceiling */ in armSignedSatQ() argument
1645 Int ceil = (1 << (imm5-1)) - 1; // (2^(imm5-1))-1 in armSignedSatQ()
1646 Int floor = -(1 << (imm5-1)); // -(2^(imm5-1)) in armSignedSatQ()
2389 UInt sh2, UInt imm5, in mk_EA_reg_plusminus_shifted_reg() argument
2396 vassert(imm5 < 32); in mk_EA_reg_plusminus_shifted_reg()
2402 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5)); in mk_EA_reg_plusminus_shifted_reg()
2403 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); in mk_EA_reg_plusminus_shifted_reg()
2406 if (imm5 == 0) { in mk_EA_reg_plusminus_shifted_reg()
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| D | host_tilegx_defs.h | 206 UInt imm5; member
214 extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 );
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| D | host_arm_defs.h | 275 UInt imm5; member
284 extern ARMRI5* ARMRI5_I5 ( UInt imm5 );
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| D | host_arm_defs.c | 480 ARMRI5* ARMRI5_I5 ( UInt imm5 ) { in ARMRI5_I5() argument
483 ri5->ARMri5.I5.imm5 = imm5; in ARMRI5_I5()
484 vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed in ARMRI5_I5()
497 vex_printf("%u", ri5->ARMri5.I5.imm5); in ppARMRI5()
2785 UInt imm5 = ri->ARMri5.I5.imm5; in skeletal_RI5() local
2786 vassert(imm5 >= 1 && imm5 <= 31); in skeletal_RI5()
2788 instr |= imm5 << 7; in skeletal_RI5()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 3900 static Instr ImmPrefetchOperation(int imm5) { in ImmPrefetchOperation() argument
3901 VIXL_ASSERT(is_uint5(imm5)); in ImmPrefetchOperation()
3902 return imm5 << ImmPrefetchOperation_offset; in ImmPrefetchOperation()
4100 int imm5 = (index << (s + 1)) | (1 << s); in ImmNEON5() local
4101 return imm5 << ImmNEON5_offset; in ImmNEON5()
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| D | simulator-a64.cc | 2962 int imm5 = instr->ImmNEON5(); in VisitNEONCopy() local
2963 int tz = CountTrailingZeros(imm5, 32); in VisitNEONCopy()
2964 int reg_index = imm5 >> (tz + 1); in VisitNEONCopy()
3671 int imm5 = instr->ImmNEON5(); in VisitNEONScalarCopy() local
3672 int tz = CountTrailingZeros(imm5, 32); in VisitNEONScalarCopy()
3673 int rn_index = imm5 >> (tz + 1); in VisitNEONScalarCopy()
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| D | disasm-a64.cc | 3075 int imm5 = instr->ImmNEON5(); in SubstituteImmediateField() local
3077 int tz = CountTrailingZeros(imm5, 32); in SubstituteImmediateField()
3078 rd_index = imm5 >> (tz + 1); in SubstituteImmediateField()
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| /external/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 3191 uint32_t imm5; // encoding for the shift amount in EmulateShiftImm() local
3214 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3225 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3233 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3240 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3249 uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
4819 uint32_t imm5 = Bits32 (opcode, 11, 7); in EmulateSTRRegister() local
4820 shift_n = DecodeImmShift(typ, imm5, shift_t); in EmulateSTRRegister()
6015 uint32_t imm5 = Bits32 (opcode, 11, 7); in EmulateLDRRegister() local
6016 shift_n = DecodeImmShift (type, imm5, shift_t); in EmulateLDRRegister()
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 2860 int imm5 = 32 - fraction_bits; in vcvt_f64_s32() local
2861 int i = imm5 & 1; in vcvt_f64_s32()
2862 int imm4 = (imm5 >> 1) & 0xf; in vcvt_f64_s32()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 5721 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5727 let Inst{20-16} = imm5;
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| /external/valgrind/none/tests/arm/ |
| D | v6intThumb.stdout.exp | 757 LSLS-16 Rd, Rm, imm5
782 LSRS-16 Rd, Rm, imm5
807 ASRS-16 Rd, Rm, imm5
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