| /external/v8/test/cctest/compiler/ |
| D | instruction-selector-tester.h | 97 immediates.assign(sequence.immediates().begin(),
98 sequence.immediates().end());
103 CHECK(i < immediates.size()); in ToInt32()
105 return immediates[i].ToInt32(); in ToInt32()
111 std::deque<Constant> immediates; variable
|
| /external/mesa3d/src/gallium/auxiliary/draw/ |
| D | draw_vs_ppc.c | 127 (float (*)[4]) shader->base.immediates, in vs_ppc_run_linear()
163 align_free( (void *) shader->base.immediates ); in vs_ppc_delete()
193 vs->base.immediates = align_malloc(TGSI_EXEC_NUM_IMMEDIATES * 4 * in draw_create_vs_ppc()
205 (float (*)[4]) vs->base.immediates, in draw_create_vs_ppc()
|
| D | draw_vs.h | 118 const float (*immediates)[4]; member
|
| /external/llvm/test/CodeGen/ARM/ |
| D | inlineasm-imm-arm.ll | 15 ; Test ARM-mode "K" constraint, for bitwise inverted Data Processing immediates.
21 ; Test ARM-mode "L" constraint, for negated Data Processing immediates.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | addsub.ll | 10 ; Add pure 12-bit immediates:
55 ; Add 12-bit immediates, shifted left by 12 bits
72 ; Subtract 12-bit immediates
89 ; Subtract 12-bit immediates, shifted left by 12 bits
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | inlineasm-imm-thumb.ll | 9 ; Test Thumb-mode "J" constraint, for negated ADD immediates.
21 ; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
|
| /external/llvm/test/MC/ARM/ |
| D | thumb-diagnostics.s | 29 @ Out of range immediates for ASR instruction.
35 @ Out of range immediates for BKPT instruction.
45 @ Out of range immediates for v8 HLT instruction.
153 @ Out of range immediates for LSL instruction.
170 @ Out of range immediates for STR instruction.
220 @ B/Bcc - out of range immediates for Thumb1 branches
|
| D | thumb2-diagnostics.s | 32 @ Out of range immediates for MRC/MRC2/MRRC/MRRC2
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_ppc.h | 44 float (*immediates)[4],
|
| /external/vixl/doc/ |
| D | changelog.md | 51 + Generate better code for immediates passed to shift-capable instructions.
81 negative immediates.
82 + Added support for using `movn` when generating immediates.
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc32-ba.s | 3 # Check that large immediates in 32bit mode are accepted.
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | fold-li.ll | 4 ;; Test that immediates are folded into these instructions correctly.
|
| D | subc.ll | 1 ; All of these should be codegen'd without loading immediates
|
| D | addc.ll | 1 ; All of these should be codegen'd without loading immediates
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-optional-hash.s | 15 ; FP immediates
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZOperands.td | 219 // i32 immediates
242 // Short immediates
271 // Full 32-bit immediates. we need both signed and unsigned versions
280 // 64-bit immediates
339 // Short immediates.
371 // Floating-point immediates
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi.h | 370 LLVMValueRef immediates[LP_MAX_TGSI_IMMEDIATES][TGSI_NUM_CHANNELS]; member
456 LLVMValueRef immediates[LP_MAX_TGSI_IMMEDIATES]; member
|
| /external/llvm/test/Transforms/ConstantHoisting/X86/ |
| D | large-immediate.ll | 29 ; Check that we don't hoist immediates with small values.
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.cpp | 1621 insn->immediates[insn->numImmediatesConsumed] = imm8; in readImmediate()
1626 insn->immediates[insn->numImmediatesConsumed] = imm16; in readImmediate()
1631 insn->immediates[insn->numImmediatesConsumed] = imm32; in readImmediate()
1636 insn->immediates[insn->numImmediatesConsumed] = imm64; in readImmediate()
1739 insn->immediates[insn->numImmediatesConsumed] = in readOperands()
1740 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; in readOperands()
|
| /external/llvm/test/CodeGen/Hexagon/vect/ |
| D | vect-cst-v4i32.ll | 2 ; This one should generate a combine with two immediates.
|
| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 358 exec_list immediates; member in glsl_to_tgsi_visitor
881 foreach_iter(exec_list_iterator, iter, this->immediates) { in add_constant()
894 this->immediates.push_tail(entry); in add_constant()
3702 memcpy(&v->immediates, &original->immediates, sizeof(v->immediates)); in get_pixel_transfer_visitor()
3833 memcpy(&v->immediates, &original->immediates, sizeof(v->immediates)); in get_bitmap_visitor()
3894 struct ureg_src *immediates; member
4075 return t->immediates[index]; in src_register()
4739 t->immediates = (struct ureg_src *)CALLOC(program->num_immediates * sizeof(struct ureg_src)); in st_translate_program()
4740 if (t->immediates == NULL) { in st_translate_program()
4745 foreach_iter(exec_list_iterator, iter, program->immediates) { in st_translate_program()
[all …]
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_setup_tgsi_llvm.c | 128 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype); in emit_fetch_immediate()
666 bld->immediates[off->Index][off->SwizzleX], in txf_fetch_args()
669 bld->immediates[off->Index][off->SwizzleY], in txf_fetch_args()
672 bld->immediates[off->Index][off->SwizzleZ], in txf_fetch_args()
944 ctx->soa.immediates[ctx->soa.num_immediates][i] = in emit_immediate()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstr64Bit.td | 57 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
58 // immediates may require more code. There may be a point where it is
64 // The ALU instructions want their simm13 operands as i32 immediates.
73 // All unsigned i32 immediates can be handled by sethi+or.
78 // All negative i33 immediates can be handled by sethi+xor.
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| D | TODO | 35 - Replace constants and immediates which are 0,1,-1 or a combination of those with a swizzle.
|
| D | i915_fpc.h | 58 float immediates[I915_MAX_CONSTANT][4]; member
|