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Searched refs:instrs (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td125 def : InstRW<[WriteI], (instrs COPY)>;
131 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
132 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
148 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
154 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
155 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
551 def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>;
552 def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>;
558 def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>;
559 def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>;
[all …]
DAArch64SchedCyclone.td114 def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
125 def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>;
272 def : InstRW<[WriteST, WriteST], (instrs STPQi)>;
290 def : InstRW<[WriteI], (instrs ISB)>;
334 def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
350 def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;
431 def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>;
432 def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>;
439 def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32,
443 def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64,
[all …]
DAArch64SchedA53.td199 def : InstRW<[WriteI], (instrs COPY)>;
284 def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
285 def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
/external/valgrind/lackey/tests/
Dtrue.stderr.exp16 guest instrs : SB entered = ... : ...
/external/llvm/test/CodeGen/PowerPC/
Diabs.ll3 ; RUN: grep "4 .*Number of machine instrs printed"
Drlwimi3.ll3 ; RUN: grep "Number of machine instrs printed" | grep 12
/external/llvm/test/Assembler/
DConstantExprFoldCast.ll12 ; Test folding of binary instrs
/external/valgrind/coregrind/m_debuginfo/
Dreaddwarf.c3587 static void show_CF_instructions ( DiCursor instrs, Int ilen, in show_CF_instructions() argument
3594 i += show_CF_instruction( ML_(cur_plus)(instrs, i), in show_CF_instructions()
3606 UnwindContext* ctx, DiCursor instrs, Int ilen, in run_CF_instructions() argument
3622 if (0) (void)show_CF_instruction( ML_(cur_plus)(instrs,i), adi, in run_CF_instructions()
3624 j = run_CF_instruction( ctx, ML_(cur_plus)(instrs,i), in run_CF_instructions()
3670 DiCursor instrs; member
3684 cie->instrs = DiCursor_INVALID; in init_CIE()
3932 the_CIEs[this_CIE].instrs = ML_(cur_plus)(data, length); in ML_()
3943 the_CIEs[this_CIE].instrs = DiCursor_INVALID; in ML_()
3969 if (!ML_(cur_is_valid)(the_CIEs[this_CIE].instrs)) { in ML_()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td100 // 3 instrs:
105 // 4 instrs:
110 // 5 instrs:
117 // Worst case is 6 instrs:
/external/llvm/include/llvm/IR/
DInstruction.def133 HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs
/external/elfutils/src/libcpu/
Di386_parse.y247 spec: masks kPERCPERC '\n' instrs
282 instrs: instrs '\n' instr
/external/llvm/lib/Target/ARM/
DREADME-Thumb.txt14 instrs with a single register.
DARM.td100 "Prefer 32-bit Thumb instrs">;
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td551 // This pseudo instr gets expanded into 2 mtc1 instrs after register
562 // This pseudo instr gets expanded into 2 mfc1 instrs after register
/external/valgrind/cachegrind/
Dcg_main.c154 InstrInfo instrs[0]; member
680 i_node = &cgs->sbInfo->instrs[ cgs->sbInfo_i ]; in setup_InstrInfo()
/external/valgrind/callgrind/
Dmain.c862 /*INOUT*/ UInt* instrs, in CLG_()
887 (*instrs)++; in CLG_()
/external/llvm/lib/Target/PowerPC/
DREADME.txt370 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
DPPCInstrQPX.td99 let FastIselShouldIgnore = 1 in // FastIsel should ignore all u12 instrs.
DPPCInstr64Bit.td339 // 64-bit SPR manipulation instrs.
/external/llvm/include/llvm/Target/
DTargetSchedule.td59 def instrs;
/external/antlr/antlr-3.4/lib/
Dantlr-3.4-complete.jarMETA-INF/ META-INF/MANIFEST.MF org/ org/antlr/ org/ ...