| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 261 bool isBranch() const { in isBranch() function
276 return isBranch() & !isBarrier() & !isIndirectBranch(); in isConditionalBranch()
284 return isBranch() & isBarrier() & !isIndirectBranch(); in isUnconditionalBranch()
291 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
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| D | MCInstrAnalysis.h | 34 virtual bool isBranch(const MCInst &Inst) const { in isBranch() function
35 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 61 if (!MCID->isBranch()) in isBCTRAfterSet()
178 if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) { in EmitInstruction()
199 if (MCID->isBranch()) in EmitInstruction()
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| D | PPCEarlyReturn.cpp | 118 } else if (J->isBranch()) { in processBlock()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 205 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, in tryAddingSymbolicOperand() argument
209 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, in tryAddingSymbolicOperand()
295 bool isBranch = false; in translateImmediate() local
298 isBranch = true; in translateImmediate()
551 isBranch = true; in translateImmediate()
558 isBranch = true; in translateImmediate()
568 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation, in translateImmediate()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 165 if (MI->isBranch() && !MI->isBarrier()) in isUnpredicatedTerminator()
192 if (!I->isBranch()) in AnalyzeBranch()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrTSX.td | 26 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
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| D | X86InstrControl.td | 59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
102 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
119 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 435 bool isBranch(QueryType Type = AnyInBundle) const {
450 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
458 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.cpp | 98 if (!I->isBranch()) in AnalyzeBranch()
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| D | BPFInstrInfo.td | 128 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
375 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 170 let isBranch = 1;
406 let isBranch = 1;
416 let isBranch = 1;
435 let isBranch = 1;
448 let isBranch = 1;
547 let isBranch = 1;
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| D | MipsDelaySlotFiller.cpp | 309 if (MI.isBranch()) { in init()
654 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) && in searchRange()
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| D | MipsInstrInfo.td | 295 bit isBranch = 1;
730 let isBranch = 1;
742 let isBranch = 1;
778 let isBranch = 1;
795 let isBranch = 1;
840 let isBranch = 1;
1339 let isBranch = 1;
1500 let isBranch=1;
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| D | Mips16InstrInfo.td | 509 bit isBranch = 1;
515 bit isBranch = 1;
753 let isBranch=1;
765 let isBranch = 1;
773 let isBranch = 1;
780 let isBranch = 1;
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| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 343 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, in tryAddingSymbolicOperand() argument
348 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, in tryAddingSymbolicOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 125 bool isBranch(const MachineInstr *MI) const;
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| D | HexagonInstrInfo.cpp | 714 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const { in isBranch() function in HexagonInstrInfo
715 return MI->getDesc().isBranch(); in isBranch()
1570 if (isNewValue(MI) && isBranch(MI)) in isNewValueJump()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_debug.cpp | 359 if (TID.isBranch()) {
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 622 let isBranch = 1, isTerminator = 1 in {
648 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
676 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
957 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
962 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
967 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
972 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
1106 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 225 bool isBranch : 1; variable
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 204 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { in InsertITInstructions()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 578 let isBranch = 1;
588 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
614 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
618 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
643 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
668 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 855 KillMI->isBranch() || KillMI->isTerminator()) in rescheduleMIBelowKill()
914 OtherMI->isBranch() || OtherMI->isTerminator()) in rescheduleMIBelowKill()
1093 OtherMI->isBranch() || OtherMI->isTerminator()) in rescheduleKillAboveMI()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstructions.td | 608 let isBranch = 1 in {
651 } // End isBranch = 1
977 let isBranch = 1, isTerminator = 1 in {
991 } // end isBranch = 1, isTerminator = 1
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