| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 172 bool isZExt);
174 unsigned Alignment = 0, bool isZExt = true,
183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
963 unsigned Alignment, bool isZExt, bool allocReg) { in ARMEmitLoad() argument
975 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
977 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
979 if (isZExt) { in ARMEmitLoad()
994 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
996 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
998 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
[all …]
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| D | ARMISelLowering.cpp | 6178 Entry.isZExt = false; in LowerFSINCOS()
6185 Entry.isZExt = false; in LowerFSINCOS()
10778 Entry.isZExt = !isSigned; in LowerDivRem()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1242 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
1245 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
1292 bool isZExt = isa<ZExtInst>(I); in selectIntExt() local
1309 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1383 bool isZExt) { in emitIntExt() argument
1385 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
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| D | MipsISelLowering.cpp | 2342 else if (ArgFlags.isZExt()) in CC_MipsO32()
2354 else if (ArgFlags.isZExt()) in CC_MipsO32()
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| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 63 bool isZExt() const { return Flags & ZExt; } in isZExt() function
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| D | TargetLowering.h | 2223 bool isZExt : 1; member
2232 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2056 Entry.isZExt = !isSigned; in ExpandLibCall()
2104 Entry.isZExt = !isSigned; in ExpandLibCall()
2138 Entry.isZExt = !isSigned; in ExpandChainLibCall()
2265 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2274 Entry.isZExt = !isSigned; in ExpandDivRemLibCall()
2370 Entry.isZExt = false; in ExpandSinCosLibCall()
2378 Entry.isZExt = false; in ExpandSinCosLibCall()
2386 Entry.isZExt = false; in ExpandSinCosLibCall()
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| D | LegalizeTypes.cpp | 1077 Entry.isZExt = !isSigned; in ExpandChainLibCall()
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| D | TargetLowering.cpp | 73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); in setAttributes()
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); in makeLibCall()
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| D | SelectionDAGBuilder.cpp | 7186 Entry.isZExt = false; in LowerCallTo()
7241 if (Args[i].isZExt) in LowerCallTo()
7286 else if (Args[i].isZExt) in LowerCallTo()
7305 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt)) in LowerCallTo()
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| D | LegalizeIntegerTypes.cpp | 2377 Entry.isZExt = false; in ExpandIntRes_XMULO()
2385 Entry.isZExt = false; in ExpandIntRes_XMULO()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 125 else if (ArgFlags.isZExt()) in CC_Hexagon_VarArg()
163 else if (ArgFlags.isZExt()) in CC_Hexagon()
244 else if (ArgFlags.isZExt()) in RetCC_Hexagon()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
3726 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
3729 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
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| D | AArch64ISelLowering.cpp | 1695 Entry.isZExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 315 else if (ArgFlags.isZExt()) in AnalyzeArguments()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1023 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1034 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
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| D | X86ISelLowering.cpp | 15989 Entry.isZExt = false; in LowerWin64_i128OP()
17144 Entry.isZExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 151 bool isZExt, unsigned DestReg);
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| D | PPCISelLowering.cpp | 2834 else if (Flags.isZExt()) in extendArgForPPC64()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1286 if (Outs[OIdx].Flags.isZExt()) in LowerCall()
|