Searched refs:mfhi (Results 1 – 25 of 86) sorted by relevance
1234
| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 75 ; ACC32: mfhi $2
76 ; ACC64: mfhi $2
128 ; ACC32: mfhi $2
129 ; ACC64: mfhi $2
145 ; ACC32: mfhi $[[R0:[0-9]+]]
152 ; ACC64: mfhi $[[R0:[0-9]+]]
186 ; ACC32: mfhi $[[R0:[0-9]+]]
193 ; ACC64: mfhi $[[R0:[0-9]+]]
267 ; ACC64: mfhi $2
312 ; ACC64: mfhi $2
[all …]
|
| D | mips64muldiv.ll | 32 ; ACC: mfhi $[[T1:[0-9]+]]
65 ; ACC: mfhi $2
75 ; ACC: mfhi $2
|
| D | madd-msub.ll | 23 ; DSP-DAG: mfhi $2, $[[AC]]
69 ; DSP-DAG: mfhi $2, $[[AC]]
107 ; DSP-DAG: mfhi $2, $[[AC]]
148 ; DSP-DAG: mfhi $2, $[[AC]]
194 ; DSP-DAG: mfhi $2, $[[AC]]
234 ; DSP-DAG: mfhi $2, $[[AC]]
|
| D | rem.ll | 14 ; 16: mfhi ${{[0-9]+}}
|
| D | mulll.ll | 14 ; 16: mfhi ${{[0-9]+}}
|
| D | remu.ll | 14 ; 16: mfhi ${{[0-9]+}}
|
| D | div_rem.ll | 17 ; 16: mfhi ${{[0-9]+}}
|
| D | divu_remu.ll | 18 ; 16: mfhi ${{[0-9]+}}
|
| D | mulull.ll | 15 ; 16: mfhi ${{[0-9]+}}
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | srem.ll | 37 ; NOT-R6: mfhi $[[T0:[0-9]+]]
56 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
62 ; R2-R5: mfhi $[[T0:[0-9]+]]
79 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
85 ; R2-R5: mfhi $[[T0:[0-9]+]]
102 ; NOT-R6: mfhi $2
119 ; GP64-NOT-R6: mfhi $2
|
| D | urem.ll | 39 ; NOT-R6: mfhi $[[T2:[0-9]+]]
62 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
70 ; R2-R5: mfhi $[[T2:[0-9]+]]
91 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]]
99 ; R2-R5: mfhi $[[T3:[0-9]+]]
118 ; NOT-R6: mfhi $2
135 ; GP64-NOT-R6: mfhi $2
|
| D | mul.ll | 160 ; M2: mfhi $4
166 ; 32R1-R5: mfhi $[[T0:[0-9]+]]
203 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
|
| /external/llvm/test/MC/Mips/ |
| D | mips-dsp-instructions.s | 35 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
46 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
83 mfhi $14, $ac1
94 mfhi $14
|
| D | micromips-16-bit-instructions.s | 43 # CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
98 # CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
151 mfhi $9
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 15 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips2.s | 21 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
22 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/v8/test/cctest/ |
| D | test-disasm-mips.cc | 407 COMPARE(mfhi(a0), in TEST()
409 COMPARE(mfhi(s2), in TEST()
411 COMPARE(mfhi(t4), in TEST()
413 COMPARE(mfhi(v1), in TEST()
|
| D | test-disasm-mips64.cc | 560 COMPARE(mfhi(a0), in TEST()
562 COMPARE(mfhi(s2), in TEST()
564 COMPARE(mfhi(t0), in TEST()
566 COMPARE(mfhi(v1), in TEST()
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 14 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips1.s | 18 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
19 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips2.s | 24 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
25 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| D | invalid-mips64.s | 23 …mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
24 …mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips-dsp.txt | 3 # CHECK: mfhi $21, $ac3
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 62 mfhi $s3
63 mfhi $sp
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 82 mfhi $s3
83 mfhi $sp
|
1234