1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
6; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
8; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
10; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
12; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
13; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
14; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
15; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
16; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
17; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
18; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
19; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
20; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
21; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
23; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
24; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
25; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
26; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
27; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
28; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
29; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
30
31define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
32entry:
33; ALL-LABEL: urem_i1:
34
35  ; NOT-R6:       andi    $[[T0:[0-9]+]], $5, 1
36  ; NOT-R6:       andi    $[[T1:[0-9]+]], $4, 1
37  ; NOT-R6:       divu    $zero, $[[T1]], $[[T0]]
38  ; NOT-R6:       teq     $[[T0]], $zero, 7
39  ; NOT-R6:       mfhi    $[[T2:[0-9]+]]
40  ; NOT-R6:       sll     $[[T3:[0-9]+]], $[[T2]], 31
41  ; NOT-R6:       sra     $2, $[[T3]], 31
42
43  ; R6:           andi    $[[T0:[0-9]+]], $5, 1
44  ; R6:           andi    $[[T1:[0-9]+]], $4, 1
45  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
46  ; R6:           teq     $[[T0]], $zero, 7
47  ; R6:           sll     $[[T3:[0-9]+]], $[[T2]], 31
48  ; R6:           sra     $2, $[[T3]], 31
49
50  %r = urem i1 %a, %b
51  ret i1 %r
52}
53
54define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
55entry:
56; ALL-LABEL: urem_i8:
57
58  ; NOT-R2-R6:    andi    $[[T0:[0-9]+]], $5, 255
59  ; NOT-R2-R6:    andi    $[[T1:[0-9]+]], $4, 255
60  ; NOT-R2-R6:    divu    $zero, $[[T1]], $[[T0]]
61  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
62  ; NOT-R2-R6:    mfhi    $[[T2:[0-9]+]]
63  ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 24
64  ; NOT-R2-R6:    sra     $2, $[[T3]], 24
65
66  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 255
67  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 255
68  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
69  ; R2-R5:        teq     $[[T0]], $zero, 7
70  ; R2-R5:        mfhi    $[[T2:[0-9]+]]
71  ; R2-R5:        seb     $2, $[[T2]]
72
73  ; R6:           andi    $[[T0:[0-9]+]], $5, 255
74  ; R6:           andi    $[[T1:[0-9]+]], $4, 255
75  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
76  ; R6:           teq     $[[T0]], $zero, 7
77  ; R6:           seb     $2, $[[T2]]
78
79  %r = urem i8 %a, %b
80  ret i8 %r
81}
82
83define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
84entry:
85; ALL-LABEL: urem_i16:
86
87  ; NOT-R2-R6:    andi    $[[T0:[0-9]+]], $5, 65535
88  ; NOT-R2-R6:    andi    $[[T1:[0-9]+]], $4, 65535
89  ; NOT-R2-R6:    divu    $zero, $[[T1]], $[[T0]]
90  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
91  ; NOT-R2-R6:    mfhi    $[[T2:[0-9]+]]
92  ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 16
93  ; NOT-R2-R6:    sra     $2, $[[T3]], 16
94
95  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 65535
96  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 65535
97  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
98  ; R2-R5:        teq     $[[T0]], $zero, 7
99  ; R2-R5:        mfhi    $[[T3:[0-9]+]]
100  ; R2-R5:        seh     $2, $[[T2]]
101
102  ; R6:           andi    $[[T0:[0-9]+]], $5, 65535
103  ; R6:           andi    $[[T1:[0-9]+]], $4, 65535
104  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
105  ; R6:           teq     $[[T0]], $zero, 7
106  ; R6:           seh     $2, $[[T2]]
107
108  %r = urem i16 %a, %b
109  ret i16 %r
110}
111
112define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
113entry:
114; ALL-LABEL: urem_i32:
115
116  ; NOT-R6:       divu    $zero, $4, $5
117  ; NOT-R6:       teq     $5, $zero, 7
118  ; NOT-R6:       mfhi    $2
119
120  ; R6:           modu    $2, $4, $5
121  ; R6:           teq     $5, $zero, 7
122
123  %r = urem i32 %a, %b
124  ret i32 %r
125}
126
127define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
128entry:
129; ALL-LABEL: urem_i64:
130
131  ; GP32:         lw      $25, %call16(__umoddi3)($gp)
132
133  ; GP64-NOT-R6:  ddivu   $zero, $4, $5
134  ; GP64-NOT-R6:  teq     $5, $zero, 7
135  ; GP64-NOT-R6:  mfhi    $2
136
137  ; 64R6:         dmodu   $2, $4, $5
138  ; 64R6:         teq     $5, $zero, 7
139
140  %r = urem i64 %a, %b
141  ret i64 %r
142}
143
144define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
145entry:
146  ; ALL-LABEL: urem_i128:
147
148    ; GP32:         lw      $25, %call16(__umodti3)($gp)
149
150    ; GP64-NOT-R6:  ld      $25, %call16(__umodti3)($gp)
151    ; 64-R6:        ld      $25, %call16(__umodti3)($gp)
152
153    %r = urem i128 %a, %b
154    ret i128 %r
155}
156