Searched refs:mflo (Results 1 – 25 of 90) sorted by relevance
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 31 ; M2: mflo $[[T0:[0-9]+]]
44 ; M4: mflo $[[T0:[0-9]+]]
65 ; M2: mflo $[[T0:[0-9]+]]
80 ; M4: mflo $[[T0:[0-9]+]]
102 ; M2: mflo $[[T0:[0-9]+]]
117 ; M4: mflo $[[T0:[0-9]+]]
139 ; M2: mflo $2
155 ; M2: mflo $[[T0:[0-9]+]]
157 ; M2: mflo $[[T1:[0-9]+]]
159 ; M2: mflo $3
[all …]
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| D | sdiv.ll | 34 ; NOT-R6: mflo $[[T0:[0-9]+]]
55 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
62 ; R2-R5: mflo $[[T0:[0-9]+]]
81 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
88 ; R2-R5: mflo $[[T0:[0-9]+]]
107 ; NOT-R6: mflo $2
124 ; GP64-NOT-R6: mflo $2
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| D | udiv.ll | 34 ; NOT-R6: mflo $2
49 ; NOT-R6: mflo $2
64 ; NOT-R6: mflo $2
79 ; NOT-R6: mflo $2
96 ; GP64-NOT-R6: mflo $2
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| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 48 ; ACC32: mflo $2
49 ; ACC64: mflo $2
102 ; ACC32: mflo $2
103 ; ACC64: mflo $2
144 ; ACC32: mflo $2
151 ; ACC64: mflo $2
185 ; ACC32: mflo $2
192 ; ACC64: mflo $2
244 ; ACC64: mflo $2
290 ; ACC64: mflo $2
[all …]
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| D | mulll.ll | 16 ; 16: mflo ${{[0-9]+}}
18 ; 16: mflo ${{[0-9]+}}
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| D | mulull.ll | 17 ; 16: mflo ${{[0-9]+}}
19 ; 16: mflo ${{[0-9]+}}
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| D | mips64muldiv.ll | 15 ; ACC: mflo $2
45 ; ACC: mflo $2
55 ; ACC: mflo $2
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| D | madd-msub.ll | 24 ; DSP-DAG: mflo $3, $[[AC]]
70 ; DSP-DAG: mflo $3, $[[AC]]
108 ; DSP-DAG: mflo $3, $[[AC]]
149 ; DSP-DAG: mflo $3, $[[AC]]
195 ; DSP-DAG: mflo $3, $[[AC]]
235 ; DSP-DAG: mflo $3, $[[AC]]
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| D | inlineasm-cnstrnt-reg.ll | 34 ; after the inline expression for a mflo to pull the value out of lo.
39 ; CHECK-NEXT: mflo ${{[0-9]+}}
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| D | divu.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | mul.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | div.ll | 13 ; 16: mflo ${{[0-9]+}}
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| D | div_rem.ll | 16 ; 16: mflo ${{[0-9]+}}
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| D | divu_remu.ll | 17 ; 16: mflo ${{[0-9]+}}
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| D | mips64instrs.ll | 121 ; ACCMULDIV: mflo $2
142 ; ACCMULDIV: mflo $2
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| D | 2008-08-01-AsmInline.ll | 9 ; CHECK: mflo
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| /external/llvm/test/MC/Mips/ |
| D | mips-dsp-instructions.s | 36 # CHECK: mflo $15, $ac0 # encoding: [0x00,0x00,0x78,0x12]
47 # CHECK: mflo $15 # encoding: [0x00,0x00,0x78,0x12]
84 mflo $15, $ac0
95 mflo $15
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| D | micromips-16-bit-instructions.s | 44 # CHECK-EL: mflo $9 # encoding: [0x49,0x46]
99 # CHECK-EB: mflo $9 # encoding: [0x46,0x49]
152 mflo $9
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| D | elf-gprel-32-64.s | 52 mflo $3
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| D | do_switch3.s | 44 mflo $2
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| /external/v8/test/cctest/ |
| D | test-disasm-mips.cc | 415 COMPARE(mflo(a0), in TEST()
417 COMPARE(mflo(s2), in TEST()
419 COMPARE(mflo(t4), in TEST()
421 COMPARE(mflo(v1), in TEST()
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| D | test-disasm-mips64.cc | 568 COMPARE(mflo(a0), in TEST()
570 COMPARE(mflo(s2), in TEST()
572 COMPARE(mflo(t0), in TEST()
574 COMPARE(mflo(v1), in TEST()
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| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips-dsp.txt | 6 # CHECK: mflo $21, $ac3
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| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 17 …mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 16 …mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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